From patchwork Tue Aug 30 12:18:59 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: nagabhushana.netagunte@ti.com X-Patchwork-Id: 112275 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 6C319B6F7D for ; Tue, 30 Aug 2011 22:19:11 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E6CA6280B4; Tue, 30 Aug 2011 14:19:09 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id T2JwXt5hKdjV; Tue, 30 Aug 2011 14:19:09 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7A09B280BF; Tue, 30 Aug 2011 14:19:08 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 71C73280BF for ; Tue, 30 Aug 2011 14:19:06 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id xCrR7hUA6HGw for ; Tue, 30 Aug 2011 14:19:05 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from comal.ext.ti.com (comal.ext.ti.com [198.47.26.152]) by theia.denx.de (Postfix) with ESMTPS id 067FC280B4 for ; Tue, 30 Aug 2011 14:19:04 +0200 (CEST) Received: from dbdp20.itg.ti.com ([172.24.170.38]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id p7UCJ0ib029048 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Tue, 30 Aug 2011 07:19:03 -0500 Received: from dbde70.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id p7UCJ0wD015419 for ; Tue, 30 Aug 2011 17:49:00 +0530 (IST) Received: from dbdp31.itg.ti.com (172.24.170.98) by DBDE70.ent.ti.com (172.24.170.148) with Microsoft SMTP Server id 8.3.106.1; Tue, 30 Aug 2011 17:49:00 +0530 Received: from psplinux051.india.ti.com (psplinux051.india.ti.com [172.24.162.244]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id p7UCIxgo028408; Tue, 30 Aug 2011 17:48:59 +0530 (IST) Received: from psplinux051.india.ti.com (localhost [127.0.0.1]) by psplinux051.india.ti.com (8.13.1/8.13.1) with ESMTP id p7UCIx3X013184; Tue, 30 Aug 2011 17:48:59 +0530 Received: (from x0144960@localhost) by psplinux051.india.ti.com (8.13.1/8.13.1/Submit) id p7UCIxd2013181; Tue, 30 Aug 2011 17:48:59 +0530 From: To: Date: Tue, 30 Aug 2011 17:48:59 +0530 Message-ID: <1314706739-13152-1-git-send-email-nagabhushana.netagunte@ti.com> X-Mailer: git-send-email 1.6.2.4 MIME-Version: 1.0 Cc: Nagabhushana Netagunte , sudhakar.raj@ti.com, manjunath.hadli@ti.com Subject: [U-Boot] [PATCH] dm6446: disable cache usage due to coherency issues X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Nagabhushana Netagunte there are cache coherency issues when using the DAVINCI Ethernet driver, hence caches cant be used for dm6446 u-boot. As per new cache management framework,if the caches are not used in u-boot, it needs to be explicitly indicated through macros in config file. CACHE disable is indicated by the following macro definitions in config file, 1. CONFIG_SYS_ICACHE_OFF 2. CONFIG_SYS_DCACHE_OFF 3. CONFIG_SYS_L2CACHE_OFF Signed-off-by: Nagabhushana Netagunte --- include/configs/davinci_dvevm.h | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h index 45214fa..086a2d7 100644 --- a/include/configs/davinci_dvevm.h +++ b/include/configs/davinci_dvevm.h @@ -60,6 +60,9 @@ #define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */ #define CONFIG_SYS_HZ 1000 #define CONFIG_SOC_DM644X +#define CONFIG_SYS_ICACHE_OFF +#define CONFIG_SYS_DCACHE_OFF +#define CONFIG_SYS_L2CACHE_OFF /*====================================================*/ /* EEPROM definitions for Atmel 24C256BN SEEPROM chip */ /* on Sonata/DV_EVM board. No EEPROM on schmoogie. */