| Message ID | 20190626045147.24644-3-yamada.masahiro@socionext.com |
|---|---|
| State | Accepted |
| Commit | 92edfff6c63f08a29a5b5deb7b11121954a2f6b9 |
| Delegated to: | Masahiro Yamada |
| Headers | show |
| Series | arm64: tidy up POSITION_INDEPENDENT feature and enable it for Socionext SoCs | expand |
diff --git a/configs/uniphier_v8_defconfig b/configs/uniphier_v8_defconfig index 83f78776b7d2..3908ff80d6b0 100644 --- a/configs/uniphier_v8_defconfig +++ b/configs/uniphier_v8_defconfig @@ -1,7 +1,9 @@ CONFIG_ARM=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_INIT_SP_RELATIVE=y CONFIG_ARM_SMCCC=y CONFIG_ARCH_UNIPHIER=y -CONFIG_SYS_TEXT_BASE=0x84000000 +CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=3 CONFIG_ARCH_UNIPHIER_V8_MULTI=y
For a planned new SoC in this SoC family, the base address of the DRAM will be changed from 0x80000000 to 0x20000000. The PIE support will be useful to maintain multiple similar SoCs whose DRAM addresses are different. Now CONFIG_SYS_TEXT_BASE is not important. I just set it to 0 to ensure CONFIG_POSITION_INDEPENDENT is working. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> --- configs/uniphier_v8_defconfig | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)