| Message ID | 20190625095859.104650-2-tomas.melin@vaisala.com |
|---|---|
| State | Superseded |
| Delegated to: | Heiko Schocher |
| Headers | show |
| Series | [U-Boot,1/2] xilinx_xiic: fix fill tx fifo loop | expand |
On 6/25/19 11:59 AM, Melin Tomas wrote: > Prior to starting a new transfer, conditionally wait for bus to not > be busy. > > Reinitialise controller as otherwise operation is not stable. > For reference, see linux kernel commit: 9656eeebf3f1dd05376c4c923797369746d9a618 This should be 12 character commit SHA1 and the commit subject. > Signed-off-by: Tomas Melin <tomas.melin@vaisala.com> > --- > drivers/i2c/xilinx_xiic.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/drivers/i2c/xilinx_xiic.c b/drivers/i2c/xilinx_xiic.c > index e4ca0ab936..4c2d0edf48 100644 > --- a/drivers/i2c/xilinx_xiic.c > +++ b/drivers/i2c/xilinx_xiic.c > @@ -267,6 +267,15 @@ static void xiic_reinit(struct xilinx_xiic_priv *priv) > static int xilinx_xiic_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs) > { > int ret = 0; > + struct xilinx_xiic_priv *priv = dev_get_priv(dev); Keep this sorted in reverse xmas tree order. > + ret = wait_for_bit_8(priv->base + XIIC_SR_REG_OFFSET, > + XIIC_SR_BUS_BUSY_MASK, false, 3000, true); Why 3 seconds wait ? > + if (ret) > + return ret; > + > + xiic_reinit(priv); > > for (; nmsgs > 0; nmsgs--, msg++) { > if (msg->flags & I2C_M_RD) >
On 6/25/19 2:33 PM, Marek Vasut wrote: >> + ret = wait_for_bit_8(priv->base + XIIC_SR_REG_OFFSET, >> + XIIC_SR_BUS_BUSY_MASK, false, 3000, true); > Why 3 seconds wait ? Right, seems kernel driver uses as small as 3ms timeout here. I'll change to that and verify. thanks, Tomas
diff --git a/drivers/i2c/xilinx_xiic.c b/drivers/i2c/xilinx_xiic.c index e4ca0ab936..4c2d0edf48 100644 --- a/drivers/i2c/xilinx_xiic.c +++ b/drivers/i2c/xilinx_xiic.c @@ -267,6 +267,15 @@ static void xiic_reinit(struct xilinx_xiic_priv *priv) static int xilinx_xiic_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs) { int ret = 0; + struct xilinx_xiic_priv *priv = dev_get_priv(dev); + + ret = wait_for_bit_8(priv->base + XIIC_SR_REG_OFFSET, + XIIC_SR_BUS_BUSY_MASK, false, 3000, true); + + if (ret) + return ret; + + xiic_reinit(priv); for (; nmsgs > 0; nmsgs--, msg++) { if (msg->flags & I2C_M_RD)
Prior to starting a new transfer, conditionally wait for bus to not be busy. Reinitialise controller as otherwise operation is not stable. For reference, see linux kernel commit: 9656eeebf3f1dd05376c4c923797369746d9a618 Signed-off-by: Tomas Melin <tomas.melin@vaisala.com> --- drivers/i2c/xilinx_xiic.c | 9 +++++++++ 1 file changed, 9 insertions(+)