Message ID | 4E5C6A7D.2010909@linux.vnet.ibm.com (mailing list archive) |
---|---|
State | Not Applicable |
Headers | show |
> perf events, powerpc: Add POWER7 stalled-cycles-frontend/backend events > > Extent the POWER7 PMU driver with definitions > for generic front-end and back-end stall events. Anshuman, Can you explain what these P7 events actually are and how they relate to Ingo's original comment on this in 8f62242246351b5a4bc0c1f00c0c7003edea128a Both events limit performance: most front end stalls tend to be caused by branch misprediction or instruction fetch cachemisses, backend stalls can be caused by various resource shortages or inefficient instruction scheduling. > > Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com> > > diff --git a/arch/powerpc/kernel/power7-pmu.c b/arch/powerpc/kernel/power7-pmu.c > index 593740f..e5d2844 100644 > --- a/arch/powerpc/kernel/power7-pmu.c > +++ b/arch/powerpc/kernel/power7-pmu.c > @@ -297,6 +297,8 @@ static void power7_disable_pmc(unsigned int pmc, unsigned long mmcr[]) > > static int power7_generic_events[] = { > [PERF_COUNT_HW_CPU_CYCLES] = 0x1e, > + [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x100f8, /* GCT_NOSLOT_CYC */ eg. Is this Global Completion Table (GCT) empty? > + [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x4000a, /* CMPLU_STALL */ eg. Is this instruction completion stall? Mikey > [PERF_COUNT_HW_INSTRUCTIONS] = 2, > [PERF_COUNT_HW_CACHE_REFERENCES] = 0xc880, /* LD_REF_L1_LSU*/ > [PERF_COUNT_HW_CACHE_MISSES] = 0x400f0, /* LD_MISS_L1 */ > > -- > Anshuman Khandual > > > _______________________________________________ > Linuxppc-dev mailing list > Linuxppc-dev@lists.ozlabs.org > https://lists.ozlabs.org/listinfo/linuxppc-dev >
On Friday 09 September 2011 07:08 AM, Michael Neuling wrote: >> perf events, powerpc: Add POWER7 stalled-cycles-frontend/backend events >> >> Extent the POWER7 PMU driver with definitions >> for generic front-end and back-end stall events. > > Anshuman, > > Can you explain what these P7 events actually are and how they relate to > Ingo's original comment on this in > 8f62242246351b5a4bc0c1f00c0c7003edea128a > > Both events limit performance: most front end stalls tend to be > caused by branch misprediction or instruction fetch cachemisses, > backend stalls can be caused by various resource shortages or > inefficient instruction scheduling. > As explained in Ingo's original comment, the exact definitions of the stall events are very much processor specific as different things mean different in their respective instruction pipeline. These two Power7 raw events are the closest approximation to the concept detailed in Ingo's comment. >> >> Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com> >> >> diff --git a/arch/powerpc/kernel/power7-pmu.c b/arch/powerpc/kernel/power7-pmu.c >> index 593740f..e5d2844 100644 >> --- a/arch/powerpc/kernel/power7-pmu.c >> +++ b/arch/powerpc/kernel/power7-pmu.c >> @@ -297,6 +297,8 @@ static void power7_disable_pmc(unsigned int pmc, unsigned long mmcr[]) >> >> static int power7_generic_events[] = { >> [PERF_COUNT_HW_CPU_CYCLES] = 0x1e, >> + [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x100f8, /* GCT_NOSLOT_CYC */ > > eg. Is this Global Completion Table (GCT) empty? Yes, it means cycles when the Global Completion Table has no slots from this thread > >> + [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x4000a, /* CMPLU_STALL */ > > eg. Is this instruction completion stall? Yes, it means no groups completed and GCT not empty > > Mikey > >> [PERF_COUNT_HW_INSTRUCTIONS] = 2, >> [PERF_COUNT_HW_CACHE_REFERENCES] = 0xc880, /* LD_REF_L1_LSU*/ >> [PERF_COUNT_HW_CACHE_MISSES] = 0x400f0, /* LD_MISS_L1 */ >> >> -- >> Anshuman Khandual >> >> >> _______________________________________________ >> Linuxppc-dev mailing list >> Linuxppc-dev@lists.ozlabs.org >> https://lists.ozlabs.org/listinfo/linuxppc-dev >> > -- > To unsubscribe from this list: send the line "unsubscribe linux-kernel" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html > Please read the FAQ at http://www.tux.org/lkml/ >
In message <4E69AFCF.3040404@linux.vnet.ibm.com> you wrote: > On Friday 09 September 2011 07:08 AM, Michael Neuling wrote: > >> perf events, powerpc: Add POWER7 stalled-cycles-frontend/backend events > >> > >> Extent the POWER7 PMU driver with definitions > >> for generic front-end and back-end stall events. > > > > Anshuman, > > > > Can you explain what these P7 events actually are and how they relate to > > Ingo's original comment on this in > > 8f62242246351b5a4bc0c1f00c0c7003edea128a > > > > Both events limit performance: most front end stalls tend to be > > caused by branch misprediction or instruction fetch cachemisses, > > backend stalls can be caused by various resource shortages or > > inefficient instruction scheduling. > > > As explained in Ingo's original comment, the exact definitions of the > stall events are very much processor specific as different things mean > different in their respective instruction pipeline. These two Power7 > raw events are the closest approximation to the concept detailed in > Ingo's comment. > >> > >> Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com> > >> > >> diff --git a/arch/powerpc/kernel/power7-pmu.c b/arch/powerpc/kernel/power7 -pmu.c > >> index 593740f..e5d2844 100644 > >> --- a/arch/powerpc/kernel/power7-pmu.c > >> +++ b/arch/powerpc/kernel/power7-pmu.c > >> @@ -297,6 +297,8 @@ static void power7_disable_pmc(unsigned int pmc, unsig ned long mmcr[]) > >> > >> static int power7_generic_events[] = { > >> [PERF_COUNT_HW_CPU_CYCLES] = 0x1e, > >> + [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x100f8, /* GCT_NOSLOT_CYC */ > > > > eg. Is this Global Completion Table (GCT) empty? > Yes, it means cycles when the Global Completion Table has no slots from this thread > > > >> + [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x4000a, /* CMPLU_STALL */ > > > > eg. Is this instruction completion stall? > Yes, it means no groups completed and GCT not empty I agree, I think they match what Ingo is trying to achieve. Can you add these descriptions to the patch and resubmit please? If you can find similar events for power4/5/5+/6 that would be great too submit too. FWIW, the patch compiles and runs for me. Mikey
On Fri, 2011-09-09 at 16:26 +1000, Michael Neuling wrote: > I agree, I think they match what Ingo is trying to achieve. > > Can you add these descriptions to the patch and resubmit please? > > If you can find similar events for power4/5/5+/6 that would be great too > submit too. > > FWIW, the patch compiles and runs for me. I already put it in my next branch, but feel free to send a followup patch adding some comments if you think that's worthwhile. Cheers, Ben.
diff --git a/arch/powerpc/kernel/power7-pmu.c b/arch/powerpc/kernel/power7-pmu.c index 593740f..e5d2844 100644 --- a/arch/powerpc/kernel/power7-pmu.c +++ b/arch/powerpc/kernel/power7-pmu.c @@ -297,6 +297,8 @@ static void power7_disable_pmc(unsigned int pmc, unsigned long mmcr[]) static int power7_generic_events[] = { [PERF_COUNT_HW_CPU_CYCLES] = 0x1e, + [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x100f8, /* GCT_NOSLOT_CYC */ + [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x4000a, /* CMPLU_STALL */ [PERF_COUNT_HW_INSTRUCTIONS] = 2, [PERF_COUNT_HW_CACHE_REFERENCES] = 0xc880, /* LD_REF_L1_LSU*/ [PERF_COUNT_HW_CACHE_MISSES] = 0x400f0, /* LD_MISS_L1 */
perf events, powerpc: Add POWER7 stalled-cycles-frontend/backend events Extent the POWER7 PMU driver with definitions for generic front-end and back-end stall events. Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com>