cpu/msr: skip read-only MCG_CAP MSR
diff mbox series

Message ID 20190620034051.11108-1-alex.hung@canonical.com
State Accepted
Headers show
Series
  • cpu/msr: skip read-only MCG_CAP MSR
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Commit Message

Alex Hung June 20, 2019, 3:40 a.m. UTC
Signed-off-by: Alex Hung <alex.hung@canonical.com>
---
 src/cpu/msr/msr.c | 3 +++
 1 file changed, 3 insertions(+)

Comments

Colin King June 20, 2019, 8:08 a.m. UTC | #1
On 20/06/2019 04:40, Alex Hung wrote:
> Signed-off-by: Alex Hung <alex.hung@canonical.com>
> ---
>  src/cpu/msr/msr.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/src/cpu/msr/msr.c b/src/cpu/msr/msr.c
> index 69fd80c8..2cd51e5c 100644
> --- a/src/cpu/msr/msr.c
> +++ b/src/cpu/msr/msr.c
> @@ -265,7 +265,10 @@ static const msr_info AMD_MSRs[] = {
>  	{ "SYSENTER_ESP",		0x00000175,	0xffffffffffffffffULL, NULL },
>  	{ "SYSENTER_EIP",		0x00000176,	0xffffffffffffffffULL, NULL },
>  	 */
> +	 /*
> +	  * MCG_CAP is read-only and can differ from core to core
>  	{ "MCG_CAP",			0x00000179,	0x0000000001ff0fffULL, NULL },
> +	  */
>  	{ "MCG_STATUS",			0x0000017a,	0xffffffffffffffffULL, NULL },
>  	{ "MCG_CTL",			0x0000017b,	0xffffffffffffffffULL, NULL },
>  	{ "MTRR_PHYSBASE0",		0x00000200,	0xffffffffffffffffULL, NULL },
> 
Good catch.

Acked-by: Colin Ian King <colin.king@canonical.com>
ivanhu June 25, 2019, 10:03 a.m. UTC | #2
On 6/20/19 11:40 AM, Alex Hung wrote:
> Signed-off-by: Alex Hung <alex.hung@canonical.com>
> ---
>   src/cpu/msr/msr.c | 3 +++
>   1 file changed, 3 insertions(+)
> 
> diff --git a/src/cpu/msr/msr.c b/src/cpu/msr/msr.c
> index 69fd80c8..2cd51e5c 100644
> --- a/src/cpu/msr/msr.c
> +++ b/src/cpu/msr/msr.c
> @@ -265,7 +265,10 @@ static const msr_info AMD_MSRs[] = {
>   	{ "SYSENTER_ESP",		0x00000175,	0xffffffffffffffffULL, NULL },
>   	{ "SYSENTER_EIP",		0x00000176,	0xffffffffffffffffULL, NULL },
>   	 */
> +	 /*
> +	  * MCG_CAP is read-only and can differ from core to core
>   	{ "MCG_CAP",			0x00000179,	0x0000000001ff0fffULL, NULL },
> +	  */
>   	{ "MCG_STATUS",			0x0000017a,	0xffffffffffffffffULL, NULL },
>   	{ "MCG_CTL",			0x0000017b,	0xffffffffffffffffULL, NULL },
>   	{ "MTRR_PHYSBASE0",		0x00000200,	0xffffffffffffffffULL, NULL },
> 

Acked-by: Ivan Hu <ivan.hu@canonical.com>

Patch
diff mbox series

diff --git a/src/cpu/msr/msr.c b/src/cpu/msr/msr.c
index 69fd80c8..2cd51e5c 100644
--- a/src/cpu/msr/msr.c
+++ b/src/cpu/msr/msr.c
@@ -265,7 +265,10 @@  static const msr_info AMD_MSRs[] = {
 	{ "SYSENTER_ESP",		0x00000175,	0xffffffffffffffffULL, NULL },
 	{ "SYSENTER_EIP",		0x00000176,	0xffffffffffffffffULL, NULL },
 	 */
+	 /*
+	  * MCG_CAP is read-only and can differ from core to core
 	{ "MCG_CAP",			0x00000179,	0x0000000001ff0fffULL, NULL },
+	  */
 	{ "MCG_STATUS",			0x0000017a,	0xffffffffffffffffULL, NULL },
 	{ "MCG_CTL",			0x0000017b,	0xffffffffffffffffULL, NULL },
 	{ "MTRR_PHYSBASE0",		0x00000200,	0xffffffffffffffffULL, NULL },