From patchwork Fri Aug 26 12:51:27 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ramana Radhakrishnan X-Patchwork-Id: 111777 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 78EFFB6F8C for ; Fri, 26 Aug 2011 22:51:48 +1000 (EST) Received: (qmail 26128 invoked by alias); 26 Aug 2011 12:51:47 -0000 Received: (qmail 26118 invoked by uid 22791); 26 Aug 2011 12:51:44 -0000 X-SWARE-Spam-Status: No, hits=-2.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_LOW X-Spam-Check-By: sourceware.org Received: from mail-gw0-f47.google.com (HELO mail-gw0-f47.google.com) (74.125.83.47) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Fri, 26 Aug 2011 12:51:28 +0000 Received: by gwb11 with SMTP id 11so2881325gwb.20 for ; Fri, 26 Aug 2011 05:51:28 -0700 (PDT) MIME-Version: 1.0 Received: by 10.42.168.194 with SMTP id x2mr953911icy.42.1314363087761; Fri, 26 Aug 2011 05:51:27 -0700 (PDT) Received: by 10.231.31.4 with HTTP; Fri, 26 Aug 2011 05:51:27 -0700 (PDT) In-Reply-To: References: <4e38fd50.0a22440a.54a7.ffffb1aaSMTPIN_ADDED@mx.google.com> <4e423f63.4539e30a.4e9b.ffff9a8bSMTPIN_ADDED@mx.google.com> <4e4c7139.e97a440a.0365.2408SMTPIN_ADDED@mx.google.com> Date: Fri, 26 Aug 2011 13:51:27 +0100 Message-ID: Subject: Re: [PATCH, ARM] Generate conditional compares in Thumb2 state From: Ramana Radhakrishnan To: gcc-patches@gcc.gnu.org Cc: Jiangning Liu X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org On 19 August 2011 11:06, Ramana Radhakrishnan wrote: >> >> Regression test against cortex-M0/M3/M4 profile with "-mthumb" option >> doesn't show any new failures. > > Please test on ARM state as well and make sure there are no > regressions before committing. > Jiangning told me privately that the test-results for v7-a were fine for cross-testing for arm-eabi with C and C++. And this is what I committed cheers Ramana 2011-08-26 Jiangning Liu * config/arm/arm.md (*ior_scc_scc): Enable for Thumb2 as well. (*ior_scc_scc_cmp): Likewise (*and_scc_scc): Likewise. (*and_scc_scc_cmp): Likewise. (*and_scc_scc_nodom): Likewise. (*cmp_ite0, *cmp_ite1, *cmp_and, *cmp_ior): Handle Thumb2. 2011-08-26 Jiangning Liu * gcc.target/arm/thumb2-cond-cmp-1.c: New. * gcc.target/arm/thumb2-cond-cmp-2.c: Likewise. * gcc.target/arm/thumb2-cond-cmp-3.c: Likewise. * gcc.target/arm/thumb2-cond-cmp-4.c: Likewise. > Ok if no regressions. > > Ramana > >> >> Thanks, >> -Jiangning > Index: gcc/config/arm/arm.md =================================================================== --- gcc/config/arm/arm.md (revision 178097) +++ gcc/config/arm/arm.md (working copy) @@ -49,6 +49,15 @@ (DOM_CC_X_OR_Y 2) ] ) +;; conditional compare combination +(define_constants + [(CMP_CMP 0) + (CMN_CMP 1) + (CMP_CMN 2) + (CMN_CMN 3) + (NUM_OF_COND_CMP 4) + ] +) ;; UNSPEC Usage: ;; Note: sin and cos are no-longer used. @@ -8980,40 +8989,85 @@ (set_attr "length" "8,12")] ) -;; ??? Is it worth using these conditional patterns in Thumb-2 mode? (define_insn "*cmp_ite0" [(set (match_operand 6 "dominant_cc_register" "") (compare (if_then_else:SI (match_operator 4 "arm_comparison_operator" - [(match_operand:SI 0 "s_register_operand" "r,r,r,r") - (match_operand:SI 1 "arm_add_operand" "rI,L,rI,L")]) + [(match_operand:SI 0 "s_register_operand" + "l,l,l,r,r,r,r,r,r") + (match_operand:SI 1 "arm_add_operand" + "lPy,lPy,lPy,rI,L,rI,L,rI,L")]) (match_operator:SI 5 "arm_comparison_operator" - [(match_operand:SI 2 "s_register_operand" "r,r,r,r") - (match_operand:SI 3 "arm_add_operand" "rI,rI,L,L")]) + [(match_operand:SI 2 "s_register_operand" + "l,r,r,l,l,r,r,r,r") + (match_operand:SI 3 "arm_add_operand" + "lPy,rI,L,lPy,lPy,rI,rI,L,L")]) (const_int 0)) (const_int 0)))] - "TARGET_ARM" + "TARGET_32BIT" "* { - static const char * const opcodes[4][2] = + static const char * const cmp1[NUM_OF_COND_CMP][2] = { - {\"cmp\\t%2, %3\;cmp%d5\\t%0, %1\", - \"cmp\\t%0, %1\;cmp%d4\\t%2, %3\"}, - {\"cmp\\t%2, %3\;cmn%d5\\t%0, #%n1\", - \"cmn\\t%0, #%n1\;cmp%d4\\t%2, %3\"}, - {\"cmn\\t%2, #%n3\;cmp%d5\\t%0, %1\", - \"cmp\\t%0, %1\;cmn%d4\\t%2, #%n3\"}, - {\"cmn\\t%2, #%n3\;cmn%d5\\t%0, #%n1\", - \"cmn\\t%0, #%n1\;cmn%d4\\t%2, #%n3\"} + {\"cmp%d5\\t%0, %1\", + \"cmp%d4\\t%2, %3\"}, + {\"cmn%d5\\t%0, #%n1\", + \"cmp%d4\\t%2, %3\"}, + {\"cmp%d5\\t%0, %1\", + \"cmn%d4\\t%2, #%n3\"}, + {\"cmn%d5\\t%0, #%n1\", + \"cmn%d4\\t%2, #%n3\"} }; + static const char * const cmp2[NUM_OF_COND_CMP][2] = + { + {\"cmp\\t%2, %3\", + \"cmp\\t%0, %1\"}, + {\"cmp\\t%2, %3\", + \"cmn\\t%0, #%n1\"}, + {\"cmn\\t%2, #%n3\", + \"cmp\\t%0, %1\"}, + {\"cmn\\t%2, #%n3\", + \"cmn\\t%0, #%n1\"} + }; + static const char * const ite[2] = + { + \"it\\t%d5\", + \"it\\t%d4\" + }; + static const int cmp_idx[9] = {CMP_CMP, CMP_CMP, CMP_CMN, + CMP_CMP, CMN_CMP, CMP_CMP, + CMN_CMP, CMP_CMN, CMN_CMN}; int swap = comparison_dominates_p (GET_CODE (operands[5]), GET_CODE (operands[4])); - return opcodes[which_alternative][swap]; + output_asm_insn (cmp2[cmp_idx[which_alternative]][swap], operands); + if (TARGET_THUMB2) { + output_asm_insn (ite[swap], operands); + } + output_asm_insn (cmp1[cmp_idx[which_alternative]][swap], operands); + return \"\"; }" [(set_attr "conds" "set") - (set_attr "length" "8")] + (set_attr "arch" "t2,t2,t2,t2,t2,any,any,any,any") + (set_attr_alternative "length" + [(const_int 6) + (const_int 8) + (const_int 8) + (const_int 8) + (const_int 8) + (if_then_else (eq_attr "is_thumb" "no") + (const_int 8) + (const_int 10)) + (if_then_else (eq_attr "is_thumb" "no") + (const_int 8) + (const_int 10)) + (if_then_else (eq_attr "is_thumb" "no") + (const_int 8) + (const_int 10)) + (if_then_else (eq_attr "is_thumb" "no") + (const_int 8) + (const_int 10))])] ) (define_insn "*cmp_ite1" @@ -9021,35 +9075,81 @@ (compare (if_then_else:SI (match_operator 4 "arm_comparison_operator" - [(match_operand:SI 0 "s_register_operand" "r,r,r,r") - (match_operand:SI 1 "arm_add_operand" "rI,L,rI,L")]) + [(match_operand:SI 0 "s_register_operand" + "l,l,l,r,r,r,r,r,r") + (match_operand:SI 1 "arm_add_operand" + "lPy,lPy,lPy,rI,L,rI,L,rI,L")]) (match_operator:SI 5 "arm_comparison_operator" - [(match_operand:SI 2 "s_register_operand" "r,r,r,r") - (match_operand:SI 3 "arm_add_operand" "rI,rI,L,L")]) + [(match_operand:SI 2 "s_register_operand" + "l,r,r,l,l,r,r,r,r") + (match_operand:SI 3 "arm_add_operand" + "lPy,rI,L,lPy,lPy,rI,rI,L,L")]) (const_int 1)) (const_int 0)))] - "TARGET_ARM" + "TARGET_32BIT" "* { - static const char * const opcodes[4][2] = + static const char * const cmp1[NUM_OF_COND_CMP][2] = { - {\"cmp\\t%0, %1\;cmp%d4\\t%2, %3\", - \"cmp\\t%2, %3\;cmp%D5\\t%0, %1\"}, - {\"cmn\\t%0, #%n1\;cmp%d4\\t%2, %3\", - \"cmp\\t%2, %3\;cmn%D5\\t%0, #%n1\"}, - {\"cmp\\t%0, %1\;cmn%d4\\t%2, #%n3\", - \"cmn\\t%2, #%n3\;cmp%D5\\t%0, %1\"}, - {\"cmn\\t%0, #%n1\;cmn%d4\\t%2, #%n3\", - \"cmn\\t%2, #%n3\;cmn%D5\\t%0, #%n1\"} + {\"cmp\\t%0, %1\", + \"cmp\\t%2, %3\"}, + {\"cmn\\t%0, #%n1\", + \"cmp\\t%2, %3\"}, + {\"cmp\\t%0, %1\", + \"cmn\\t%2, #%n3\"}, + {\"cmn\\t%0, #%n1\", + \"cmn\\t%2, #%n3\"} }; + static const char * const cmp2[NUM_OF_COND_CMP][2] = + { + {\"cmp%d4\\t%2, %3\", + \"cmp%D5\\t%0, %1\"}, + {\"cmp%d4\\t%2, %3\", + \"cmn%D5\\t%0, #%n1\"}, + {\"cmn%d4\\t%2, #%n3\", + \"cmp%D5\\t%0, %1\"}, + {\"cmn%d4\\t%2, #%n3\", + \"cmn%D5\\t%0, #%n1\"} + }; + static const char * const ite[2] = + { + \"it\\t%d4\", + \"it\\t%D5\" + }; + static const int cmp_idx[9] = {CMP_CMP, CMP_CMP, CMP_CMN, + CMP_CMP, CMN_CMP, CMP_CMP, + CMN_CMP, CMP_CMN, CMN_CMN}; int swap = comparison_dominates_p (GET_CODE (operands[5]), reverse_condition (GET_CODE (operands[4]))); - return opcodes[which_alternative][swap]; + output_asm_insn (cmp1[cmp_idx[which_alternative]][swap], operands); + if (TARGET_THUMB2) { + output_asm_insn (ite[swap], operands); + } + output_asm_insn (cmp2[cmp_idx[which_alternative]][swap], operands); + return \"\"; }" [(set_attr "conds" "set") - (set_attr "length" "8")] + (set_attr "arch" "t2,t2,t2,t2,t2,any,any,any,any") + (set_attr_alternative "length" + [(const_int 6) + (const_int 8) + (const_int 8) + (const_int 8) + (const_int 8) + (if_then_else (eq_attr "is_thumb" "no") + (const_int 8) + (const_int 10)) + (if_then_else (eq_attr "is_thumb" "no") + (const_int 8) + (const_int 10)) + (if_then_else (eq_attr "is_thumb" "no") + (const_int 8) + (const_int 10)) + (if_then_else (eq_attr "is_thumb" "no") + (const_int 8) + (const_int 10))])] ) (define_insn "*cmp_and" @@ -9057,34 +9157,80 @@ (compare (and:SI (match_operator 4 "arm_comparison_operator" - [(match_operand:SI 0 "s_register_operand" "r,r,r,r") - (match_operand:SI 1 "arm_add_operand" "rI,L,rI,L")]) + [(match_operand:SI 0 "s_register_operand" + "l,l,l,r,r,r,r,r,r") + (match_operand:SI 1 "arm_add_operand" + "lPy,lPy,lPy,rI,L,rI,L,rI,L")]) (match_operator:SI 5 "arm_comparison_operator" - [(match_operand:SI 2 "s_register_operand" "r,r,r,r") - (match_operand:SI 3 "arm_add_operand" "rI,rI,L,L")])) + [(match_operand:SI 2 "s_register_operand" + "l,r,r,l,l,r,r,r,r") + (match_operand:SI 3 "arm_add_operand" + "lPy,rI,L,lPy,lPy,rI,rI,L,L")])) (const_int 0)))] - "TARGET_ARM" + "TARGET_32BIT" "* { - static const char *const opcodes[4][2] = + static const char *const cmp1[NUM_OF_COND_CMP][2] = { - {\"cmp\\t%2, %3\;cmp%d5\\t%0, %1\", - \"cmp\\t%0, %1\;cmp%d4\\t%2, %3\"}, - {\"cmp\\t%2, %3\;cmn%d5\\t%0, #%n1\", - \"cmn\\t%0, #%n1\;cmp%d4\\t%2, %3\"}, - {\"cmn\\t%2, #%n3\;cmp%d5\\t%0, %1\", - \"cmp\\t%0, %1\;cmn%d4\\t%2, #%n3\"}, - {\"cmn\\t%2, #%n3\;cmn%d5\\t%0, #%n1\", - \"cmn\\t%0, #%n1\;cmn%d4\\t%2, #%n3\"} + {\"cmp%d5\\t%0, %1\", + \"cmp%d4\\t%2, %3\"}, + {\"cmn%d5\\t%0, #%n1\", + \"cmp%d4\\t%2, %3\"}, + {\"cmp%d5\\t%0, %1\", + \"cmn%d4\\t%2, #%n3\"}, + {\"cmn%d5\\t%0, #%n1\", + \"cmn%d4\\t%2, #%n3\"} }; + static const char *const cmp2[NUM_OF_COND_CMP][2] = + { + {\"cmp\\t%2, %3\", + \"cmp\\t%0, %1\"}, + {\"cmp\\t%2, %3\", + \"cmn\\t%0, #%n1\"}, + {\"cmn\\t%2, #%n3\", + \"cmp\\t%0, %1\"}, + {\"cmn\\t%2, #%n3\", + \"cmn\\t%0, #%n1\"} + }; + static const char *const ite[2] = + { + \"it\\t%d5\", + \"it\\t%d4\" + }; + static const int cmp_idx[9] = {CMP_CMP, CMP_CMP, CMP_CMN, + CMP_CMP, CMN_CMP, CMP_CMP, + CMN_CMP, CMP_CMN, CMN_CMN}; int swap = comparison_dominates_p (GET_CODE (operands[5]), GET_CODE (operands[4])); - return opcodes[which_alternative][swap]; + output_asm_insn (cmp2[cmp_idx[which_alternative]][swap], operands); + if (TARGET_THUMB2) { + output_asm_insn (ite[swap], operands); + } + output_asm_insn (cmp1[cmp_idx[which_alternative]][swap], operands); + return \"\"; }" [(set_attr "conds" "set") (set_attr "predicable" "no") - (set_attr "length" "8")] + (set_attr "arch" "t2,t2,t2,t2,t2,any,any,any,any") + (set_attr_alternative "length" + [(const_int 6) + (const_int 8) + (const_int 8) + (const_int 8) + (const_int 8) + (if_then_else (eq_attr "is_thumb" "no") + (const_int 8) + (const_int 10)) + (if_then_else (eq_attr "is_thumb" "no") + (const_int 8) + (const_int 10)) + (if_then_else (eq_attr "is_thumb" "no") + (const_int 8) + (const_int 10)) + (if_then_else (eq_attr "is_thumb" "no") + (const_int 8) + (const_int 10))])] ) (define_insn "*cmp_ior" @@ -9092,34 +9238,80 @@ (compare (ior:SI (match_operator 4 "arm_comparison_operator" - [(match_operand:SI 0 "s_register_operand" "r,r,r,r") - (match_operand:SI 1 "arm_add_operand" "rI,L,rI,L")]) + [(match_operand:SI 0 "s_register_operand" + "l,l,l,r,r,r,r,r,r") + (match_operand:SI 1 "arm_add_operand" + "lPy,lPy,lPy,rI,L,rI,L,rI,L")]) (match_operator:SI 5 "arm_comparison_operator" - [(match_operand:SI 2 "s_register_operand" "r,r,r,r") - (match_operand:SI 3 "arm_add_operand" "rI,rI,L,L")])) + [(match_operand:SI 2 "s_register_operand" + "l,r,r,l,l,r,r,r,r") + (match_operand:SI 3 "arm_add_operand" + "lPy,rI,L,lPy,lPy,rI,rI,L,L")])) (const_int 0)))] - "TARGET_ARM" + "TARGET_32BIT" "* -{ - static const char *const opcodes[4][2] = { - {\"cmp\\t%0, %1\;cmp%D4\\t%2, %3\", - \"cmp\\t%2, %3\;cmp%D5\\t%0, %1\"}, - {\"cmn\\t%0, #%n1\;cmp%D4\\t%2, %3\", - \"cmp\\t%2, %3\;cmn%D5\\t%0, #%n1\"}, - {\"cmp\\t%0, %1\;cmn%D4\\t%2, #%n3\", - \"cmn\\t%2, #%n3\;cmp%D5\\t%0, %1\"}, - {\"cmn\\t%0, #%n1\;cmn%D4\\t%2, #%n3\", - \"cmn\\t%2, #%n3\;cmn%D5\\t%0, #%n1\"} - }; - int swap = - comparison_dominates_p (GET_CODE (operands[5]), GET_CODE (operands[4])); + static const char *const cmp1[NUM_OF_COND_CMP][2] = + { + {\"cmp\\t%0, %1\", + \"cmp\\t%2, %3\"}, + {\"cmn\\t%0, #%n1\", + \"cmp\\t%2, %3\"}, + {\"cmp\\t%0, %1\", + \"cmn\\t%2, #%n3\"}, + {\"cmn\\t%0, #%n1\", + \"cmn\\t%2, #%n3\"} + }; + static const char *const cmp2[NUM_OF_COND_CMP][2] = + { + {\"cmp%D4\\t%2, %3\", + \"cmp%D5\\t%0, %1\"}, + {\"cmp%D4\\t%2, %3\", + \"cmn%D5\\t%0, #%n1\"}, + {\"cmn%D4\\t%2, #%n3\", + \"cmp%D5\\t%0, %1\"}, + {\"cmn%D4\\t%2, #%n3\", + \"cmn%D5\\t%0, #%n1\"} + }; + static const char *const ite[2] = + { + \"it\\t%D4\", + \"it\\t%D5\" + }; + static const int cmp_idx[9] = {CMP_CMP, CMP_CMP, CMP_CMN, + CMP_CMP, CMN_CMP, CMP_CMP, + CMN_CMP, CMP_CMN, CMN_CMN}; + int swap = + comparison_dominates_p (GET_CODE (operands[5]), GET_CODE (operands[4])); - return opcodes[which_alternative][swap]; -} -" + output_asm_insn (cmp1[cmp_idx[which_alternative]][swap], operands); + if (TARGET_THUMB2) { + output_asm_insn (ite[swap], operands); + } + output_asm_insn (cmp2[cmp_idx[which_alternative]][swap], operands); + return \"\"; + } + " [(set_attr "conds" "set") - (set_attr "length" "8")] + (set_attr "arch" "t2,t2,t2,t2,t2,any,any,any,any") + (set_attr_alternative "length" + [(const_int 6) + (const_int 8) + (const_int 8) + (const_int 8) + (const_int 8) + (if_then_else (eq_attr "is_thumb" "no") + (const_int 8) + (const_int 10)) + (if_then_else (eq_attr "is_thumb" "no") + (const_int 8) + (const_int 10)) + (if_then_else (eq_attr "is_thumb" "no") + (const_int 8) + (const_int 10)) + (if_then_else (eq_attr "is_thumb" "no") + (const_int 8) + (const_int 10))])] ) (define_insn_and_split "*ior_scc_scc" @@ -9131,11 +9323,11 @@ [(match_operand:SI 4 "s_register_operand" "r") (match_operand:SI 5 "arm_add_operand" "rIL")]))) (clobber (reg:CC CC_REGNUM))] - "TARGET_ARM + "TARGET_32BIT && (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_OR_Y) != CCmode)" "#" - "TARGET_ARM && reload_completed" + "TARGET_32BIT && reload_completed" [(set (match_dup 7) (compare (ior:SI @@ -9164,9 +9356,9 @@ (set (match_operand:SI 7 "s_register_operand" "=r") (ior:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)]) (match_op_dup 6 [(match_dup 4) (match_dup 5)])))] - "TARGET_ARM" + "TARGET_32BIT" "#" - "TARGET_ARM && reload_completed" + "TARGET_32BIT && reload_completed" [(set (match_dup 0) (compare (ior:SI @@ -9187,11 +9379,11 @@ [(match_operand:SI 4 "s_register_operand" "r") (match_operand:SI 5 "arm_add_operand" "rIL")]))) (clobber (reg:CC CC_REGNUM))] - "TARGET_ARM + "TARGET_32BIT && (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_AND_Y) != CCmode)" "#" - "TARGET_ARM && reload_completed + "TARGET_32BIT && reload_completed && (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_AND_Y) != CCmode)" [(set (match_dup 7) @@ -9222,9 +9414,9 @@ (set (match_operand:SI 7 "s_register_operand" "=r") (and:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)]) (match_op_dup 6 [(match_dup 4) (match_dup 5)])))] - "TARGET_ARM" + "TARGET_32BIT" "#" - "TARGET_ARM && reload_completed" + "TARGET_32BIT && reload_completed" [(set (match_dup 0) (compare (and:SI @@ -9249,11 +9441,11 @@ [(match_operand:SI 4 "s_register_operand" "r,r,r") (match_operand:SI 5 "arm_add_operand" "rIL,rIL,rIL")]))) (clobber (reg:CC CC_REGNUM))] - "TARGET_ARM + "TARGET_32BIT && (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_AND_Y) == CCmode)" "#" - "TARGET_ARM && reload_completed" + "TARGET_32BIT && reload_completed" [(parallel [(set (match_dup 0) (match_op_dup 3 [(match_dup 1) (match_dup 2)])) (clobber (reg:CC CC_REGNUM))]) Index: gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-4.c =================================================================== --- gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-4.c (revision 0) +++ gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-4.c (revision 0) @@ -0,0 +1,12 @@ +/* Use conditional compare */ +/* { dg-options "-O2" } */ +/* { dg-skip-if "" { arm_thumb1_ok } } */ +/* { dg-final { scan-assembler "cmpgt" } } */ + +int f(int i, int j) +{ + if ( (i >= '+') ? (j <= '-') : 1) + return 1; + else + return 0; +} Index: gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-1.c =================================================================== --- gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-1.c (revision 0) +++ gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-1.c (revision 0) @@ -0,0 +1,13 @@ +/* Use conditional compare */ +/* { dg-options "-O2" } */ +/* { dg-skip-if "" { arm_thumb1_ok } } */ +/* { dg-final { scan-assembler "cmpne" } } */ + +int f(int i, int j) +{ + if ( (i == '+') || (j == '-') ) { + return 1; + } else { + return 0; + } +} Index: gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-2.c =================================================================== --- gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-2.c (revision 0) +++ gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-2.c (revision 0) @@ -0,0 +1,13 @@ +/* Use conditional compare */ +/* { dg-options "-O2" } */ +/* { dg-skip-if "" { arm_thumb1_ok } } */ +/* { dg-final { scan-assembler "cmpeq" } } */ + +int f(int i, int j) +{ + if ( (i == '+') && (j == '-') ) { + return 1; + } else { + return 0; + } +} Index: gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-3.c =================================================================== --- gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-3.c (revision 0) +++ gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-3.c (revision 0) @@ -0,0 +1,12 @@ +/* Use conditional compare */ +/* { dg-options "-O2" } */ +/* { dg-skip-if "" { arm_thumb1_ok } } */ +/* { dg-final { scan-assembler "cmpgt" } } */ + +int f(int i, int j) +{ + if ( (i >= '+') ? (j > '-') : 0) + return 1; + else + return 0; +}