From patchwork Fri Aug 26 00:37:36 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Sriraman Tallam X-Patchwork-Id: 111693 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 40215B70C6 for ; Fri, 26 Aug 2011 10:38:05 +1000 (EST) Received: (qmail 11464 invoked by alias); 26 Aug 2011 00:38:01 -0000 Received: (qmail 11456 invoked by uid 22791); 26 Aug 2011 00:37:58 -0000 X-SWARE-Spam-Status: No, hits=-1.4 required=5.0 tests=AWL, BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, RP_MATCHES_RCVD, SPF_HELO_PASS, TW_CP, TW_EB, TW_FX, TW_XF X-Spam-Check-By: sourceware.org Received: from smtp-out.google.com (HELO smtp-out.google.com) (216.239.44.51) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Fri, 26 Aug 2011 00:37:40 +0000 Received: from wpaz5.hot.corp.google.com (wpaz5.hot.corp.google.com [172.24.198.69]) by smtp-out.google.com with ESMTP id p7Q0bdVH023385 for ; Thu, 25 Aug 2011 17:37:39 -0700 Received: from ywo32 (ywo32.prod.google.com [10.192.15.32]) by wpaz5.hot.corp.google.com with ESMTP id p7Q0bO2s016559 (version=TLSv1/SSLv3 cipher=RC4-SHA bits=128 verify=NOT) for ; Thu, 25 Aug 2011 17:37:38 -0700 Received: by ywo32 with SMTP id 32so3350656ywo.27 for ; Thu, 25 Aug 2011 17:37:38 -0700 (PDT) Received: by 10.151.112.16 with SMTP id p16mr1715093ybm.119.1314319058218; Thu, 25 Aug 2011 17:37:38 -0700 (PDT) MIME-Version: 1.0 Received: by 10.151.112.16 with SMTP id p16mr1715073ybm.119.1314319056626; Thu, 25 Aug 2011 17:37:36 -0700 (PDT) Received: by 10.151.99.13 with HTTP; Thu, 25 Aug 2011 17:37:36 -0700 (PDT) In-Reply-To: References: <20110816205046.44176B21AC@azwildcat.mtv.corp.google.com> <4E4D80E3.7060803@redhat.com> <4E4D8D4A.8080602@redhat.com> <4E5020FC.1080707@redhat.com> Date: Thu, 25 Aug 2011 17:37:36 -0700 Message-ID: Subject: Re: [4.7][google]Support for getting CPU type and feature information at run-time. (issue4893046) From: Sriraman Tallam To: Michael Matz Cc: "H.J. Lu" , Richard Guenther , Richard Henderson , reply@codereview.appspotmail.com, GCC Patches X-System-Of-Record: true X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Hi, Thanks for all the comments. I am attaching a new patch incorporating all of the changes mentioned, mainly : 1) Make __cpu_indicator_init a constructor in libgcc and guard to call it only once. 2) Add symbol versions. 3) Move all builtins to the i386 port. 4) Add check for atom processor. 5) No separate passes to fold the builtins. Please let me know what you think. Thanks, -Sri. * config/i386/i386.c (build_struct_with_one_bit_fields): New function. (make_var_decl): New function. (get_field_from_struct): New function. (fold_builtin_target): New function. (ix86_fold_builtin): New function. (ix86_expand_builtin): Expand new builtins by folding them. (TARGET_FOLD_BUILTIN): New macro. (IX86_BUILTIN_CPU_SUPPORTS_CMOV): New enum value. (IX86_BUILTIN_CPU_SUPPORTS_MMX): New enum value. (IX86_BUILTIN_CPU_SUPPORTS_POPCOUNT): New enum value. (IX86_BUILTIN_CPU_SUPPORTS_SSE): New enum value. (IX86_BUILTIN_CPU_SUPPORTS_SSE2): New enum value. (IX86_BUILTIN_CPU_SUPPORTS_SSE3): New enum value. (IX86_BUILTIN_CPU_SUPPORTS_SSSE3): New enum value. (IX86_BUILTIN_CPU_SUPPORTS_SSE4_1): New enum value. (IX86_BUILTIN_CPU_SUPPORTS_SSE4_2): New enum value. (IX86_BUILTIN_CPU_IS_AMD): New enum value. (IX86_BUILTIN_CPU_IS_INTEL): New enum value. (IX86_BUILTIN_CPU_IS_INTEL_ATOM): New enum value. (IX86_BUILTIN_CPU_IS_INTEL_CORE2): New enum value. (IX86_BUILTIN_CPU_IS_INTEL_COREI7_NEHALEM): New enum value. (IX86_BUILTIN_CPU_IS_INTEL_COREI7_WESTMERE): New enum value. (IX86_BUILTIN_CPU_IS_INTEL_COREI7_SANDYBRIDGE): New enum value. (IX86_BUILTIN_CPU_IS_AMDFAM10_BARCELONA): New enum value. (IX86_BUILTIN_CPU_IS_AMDFAM10_SHANGHAI): New enum value. (IX86_BUILTIN_CPU_IS_AMDFAM10_ISTANBUL): New enum value. * config/i386/libgcc-glibc.ver (__cpu_indicator_init): Export symbol. (__cpu_model): Export symbol. (__cpu_features): Export symbol. * config/i386/i386-builtin-types.def: New function type. * config/i386/i386-cpuinfo.c: New file. * config/i386/t-cpuinfo: New file. * config.host: Add t-cpuinfo to link i386-cpuinfo.o with libgcc * gcc.dg/builtin_target.c: New test. On Tue, Aug 23, 2011 at 4:35 AM, Michael Matz wrote: > Hi, > > On Mon, 22 Aug 2011, H.J. Lu wrote: > >> > void __attribute__((constructor)) bla(void) >> > { >> >  __cpu_indicator_init (); >> > } >> > >> > I don't see any complication.? >> > >> >> Order of constructors.  A constructor may call functions >> which use __cpu_indicator. > > That's why I wrote also: > >> The initializer function has to be callable from pre-.init contexts, e.g. >> ifunc dispatchers. > > It obviously has to be guarded against multiple calls.  The ctor in libgcc > would be mere convenience because then non-ctor code can rely on the data > being initialized, and only (potential) ctor code has to check and call > the init function on demand. > > > Ciao, > Michael. Index: libgcc/config.host =================================================================== --- libgcc/config.host (revision 177767) +++ libgcc/config.host (working copy) @@ -609,7 +609,7 @@ case ${host} in i[34567]86-*-linux* | x86_64-*-linux* | \ i[34567]86-*-kfreebsd*-gnu | i[34567]86-*-knetbsd*-gnu | \ i[34567]86-*-gnu*) - tmake_file="${tmake_file} t-tls" + tmake_file="${tmake_file} t-tls i386/t-cpuinfo" if test "$libgcc_cv_cfi" = "yes"; then tmake_file="${tmake_file} t-stack i386/t-stack-i386" fi Index: libgcc/config/i386/t-cpuinfo =================================================================== --- libgcc/config/i386/t-cpuinfo (revision 0) +++ libgcc/config/i386/t-cpuinfo (revision 0) @@ -0,0 +1 @@ +LIB2ADD += $(srcdir)/config/i386/i386-cpuinfo.c Index: libgcc/config/i386/i386-cpuinfo.c =================================================================== --- libgcc/config/i386/i386-cpuinfo.c (revision 0) +++ libgcc/config/i386/i386-cpuinfo.c (revision 0) @@ -0,0 +1,245 @@ +/* Get CPU type and Features for x86 processors. + Copyright (C) 2011 Free Software Foundation, Inc. + Contributed by Sriraman Tallam (tmsriram@google.com) + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING3. If not see +. */ + +#include "cpuid.h" + +void __cpu_indicator_init (void) __attribute__ ((constructor)); + +enum vendor_signatures +{ + SIG_INTEL = 0x756e6547 /* Genu */, + SIG_AMD = 0x68747541 /* Auth */ +}; + + +/* Features supported. */ + +struct __processor_features +{ + unsigned int __cpu_cmov : 1; + unsigned int __cpu_mmx : 1; + unsigned int __cpu_popcnt : 1; + unsigned int __cpu_sse : 1; + unsigned int __cpu_sse2 : 1; + unsigned int __cpu_sse3 : 1; + unsigned int __cpu_ssse3 : 1; + unsigned int __cpu_sse4_1 : 1; + unsigned int __cpu_sse4_2 : 1; +} __cpu_features = {0}; + +/* Processor Model. */ + +struct __processor_model +{ + unsigned int __cpu_is_amd : 1; + unsigned int __cpu_is_intel : 1; + unsigned int __cpu_is_intel_atom : 1; + unsigned int __cpu_is_intel_core2 : 1; + unsigned int __cpu_is_intel_corei7_nehalem : 1; + unsigned int __cpu_is_intel_corei7_westmere : 1; + unsigned int __cpu_is_intel_corei7_sandybridge : 1; + unsigned int __cpu_is_amdfam10_barcelona : 1; + unsigned int __cpu_is_amdfam10_shanghai : 1; + unsigned int __cpu_is_amdfam10_istanbul : 1; +} __cpu_model = {0}; + +/* Get the specific type of AMD CPU. */ + +static void +get_amd_cpu (unsigned int family, unsigned int model) +{ + switch (family) + { + case 0x10: + switch (model) + { + case 0x2: + __cpu_model.__cpu_is_amdfam10_barcelona = 1; + break; + case 0x4: + __cpu_model.__cpu_is_amdfam10_shanghai = 1; + break; + case 0x8: + __cpu_model.__cpu_is_amdfam10_istanbul = 1; + break; + default: + break; + } + break; + default: + break; + } +} + +/* Get the specific type of Intel CPU. */ + +static void +get_intel_cpu (unsigned int family, unsigned int model, unsigned int brand_id) +{ + /* Parse family and model only if brand ID is 0. */ + if (brand_id == 0) + { + switch (family) + { + case 0x5: + /* Pentium. */ + break; + case 0x6: + switch (model) + { + case 0x1c: + case 0x26: + /* Atom. */ + __cpu_model.__cpu_is_intel_atom = 1; + break; + case 0x1a: + case 0x1e: + case 0x1f: + case 0x2e: + /* Nehalem. */ + __cpu_model.__cpu_is_intel_corei7_nehalem = 1; + break; + case 0x25: + case 0x2c: + case 0x2f: + /* Westmere. */ + __cpu_model.__cpu_is_intel_corei7_westmere = 1; + break; + case 0x2a: + /* Sandy Bridge. */ + __cpu_model.__cpu_is_intel_corei7_sandybridge = 1; + break; + case 0x17: + case 0x1d: + /* Penryn. */ + case 0x0f: + /* Merom. */ + __cpu_model.__cpu_is_intel_core2 = 1; + break; + default: + break; + } + break; + default: + /* We have no idea. */ + break; + } + } +} + +static void +get_available_features (unsigned int ecx, unsigned int edx) +{ + __cpu_features.__cpu_cmov = (edx & bit_CMOV) ? 1 : 0; + __cpu_features.__cpu_mmx = (edx & bit_MMX) ? 1 : 0; + __cpu_features.__cpu_sse = (edx & bit_SSE) ? 1 : 0; + __cpu_features.__cpu_sse2 = (edx & bit_SSE2) ? 1 : 0; + __cpu_features.__cpu_popcnt = (ecx & bit_POPCNT) ? 1 : 0; + __cpu_features.__cpu_sse3 = (ecx & bit_SSE3) ? 1 : 0; + __cpu_features.__cpu_ssse3 = (ecx & bit_SSSE3) ? 1 : 0; + __cpu_features.__cpu_sse4_1 = (ecx & bit_SSE4_1) ? 1 : 0; + __cpu_features.__cpu_sse4_2 = (ecx & bit_SSE4_2) ? 1 : 0; +} + +/* A noinline function calling __get_cpuid. Having many calls to + cpuid in one function in 32-bit mode causes GCC to complain: + "can’t find a register in class ‘CLOBBERED_REGS’". This is + related to PR rtl-optimization 44174. */ + +static int __attribute__ ((noinline)) +__get_cpuid_output (unsigned int __level, + unsigned int *__eax, unsigned int *__ebx, + unsigned int *__ecx, unsigned int *__edx) +{ + return __get_cpuid (__level, __eax, __ebx, __ecx, __edx); +} + + +/* A constructor function that is sets __cpu_model and __cpu_features with + the right values. This needs to run only once. + If another constructor needs to use these values, explicitly call this + function from the other constructor. Otherwise, the ordering of + constructors could make this constructor run later. */ + +void __attribute__ ((constructor)) +__cpu_indicator_init (void) +{ + unsigned int eax, ebx, ecx, edx; + + int max_level = 5; + unsigned int vendor; + unsigned int model, family, brand_id; + static int called = 0; + + /* This function needs to run just once. */ + if (called) + return; + else + called = 1; + + /* Assume cpuid insn present. Run in level 0 to get vendor id. */ + if (!__get_cpuid_output (0, &eax, &ebx, &ecx, &edx)) + return; + + vendor = ebx; + max_level = eax; + + if (max_level < 1) + return; + + if (!__get_cpuid_output (1, &eax, &ebx, &ecx, &edx)) + return; + + model = (eax >> 4) & 0x0f; + family = (eax >> 8) & 0x0f; + brand_id = ebx & 0xff; + + /* Adjust model and family for Intel CPUS. */ + if (vendor == SIG_INTEL) + { + unsigned int extended_model, extended_family; + + extended_model = (eax >> 12) & 0xf0; + extended_family = (eax >> 20) & 0xff; + if (family == 0x0f) + { + family += extended_family; + model += extended_model; + } + else if (family == 0x06) + model += extended_model; + } + + /* Find CPU model. */ + + if (vendor == SIG_AMD) + { + __cpu_model.__cpu_is_amd = 1; + get_amd_cpu (family, model); + } + else if (vendor == SIG_INTEL) + { + __cpu_model.__cpu_is_intel = 1; + get_intel_cpu (family, model, brand_id); + } + + /* Find available features. */ + get_available_features (ecx, edx); +} Index: gcc/testsuite/gcc.dg/builtin_target.c =================================================================== --- gcc/testsuite/gcc.dg/builtin_target.c (revision 0) +++ gcc/testsuite/gcc.dg/builtin_target.c (revision 0) @@ -0,0 +1,53 @@ +/* This test checks if the __builtin_cpu_* calls are recognized. */ + +/* { dg-do run } */ + +int +fn1 () +{ + if (__builtin_cpu_supports_cmov () < 0) + return -1; + if (__builtin_cpu_supports_mmx () < 0) + return -1; + if (__builtin_cpu_supports_popcount () < 0) + return -1; + if (__builtin_cpu_supports_sse () < 0) + return -1; + if (__builtin_cpu_supports_sse2 () < 0) + return -1; + if (__builtin_cpu_supports_sse3 () < 0) + return -1; + if (__builtin_cpu_supports_ssse3 () < 0) + return -1; + if (__builtin_cpu_supports_sse4_1 () < 0) + return -1; + if (__builtin_cpu_supports_sse4_2 () < 0) + return -1; + if (__builtin_cpu_is_amd () < 0) + return -1; + if (__builtin_cpu_is_intel () < 0) + return -1; + if (__builtin_cpu_is_intel_atom () < 0) + return -1; + if (__builtin_cpu_is_intel_core2 () < 0) + return -1; + if (__builtin_cpu_is_intel_corei7_nehalem () < 0) + return -1; + if (__builtin_cpu_is_intel_corei7_westmere () < 0) + return -1; + if (__builtin_cpu_is_intel_corei7_sandybridge () < 0) + return -1; + if (__builtin_cpu_is_amdfam10_barcelona () < 0) + return -1; + if (__builtin_cpu_is_amdfam10_shanghai () < 0) + return -1; + if (__builtin_cpu_is_amdfam10_istanbul () < 0) + return -1; + + return 0; +} + +int main () +{ + return fn1 (); +} Index: gcc/config/i386/i386-builtin-types.def =================================================================== --- gcc/config/i386/i386-builtin-types.def (revision 177767) +++ gcc/config/i386/i386-builtin-types.def (working copy) @@ -131,6 +131,7 @@ DEF_FUNCTION_TYPE (UINT64) DEF_FUNCTION_TYPE (UNSIGNED) DEF_FUNCTION_TYPE (VOID) DEF_FUNCTION_TYPE (PVOID) +DEF_FUNCTION_TYPE (INT) DEF_FUNCTION_TYPE (FLOAT, FLOAT) DEF_FUNCTION_TYPE (FLOAT128, FLOAT128) Index: gcc/config/i386/libgcc-glibc.ver =================================================================== --- gcc/config/i386/libgcc-glibc.ver (revision 177767) +++ gcc/config/i386/libgcc-glibc.ver (working copy) @@ -147,6 +147,12 @@ GCC_4.3.0 { __trunctfxf2 __unordtf2 } + +GCC_4.6.0 { + __cpu_indicator_init + __cpu_model + __cpu_features +} %else GCC_4.4.0 { __addtf3 @@ -183,4 +189,10 @@ GCC_4.4.0 { GCC_4.5.0 { __extendxftf2 } + +GCC_4.6.0 { + __cpu_indicator_init + __cpu_model + __cpu_features +} %endif Index: gcc/config/i386/i386.c =================================================================== --- gcc/config/i386/i386.c (revision 177767) +++ gcc/config/i386/i386.c (working copy) @@ -58,6 +58,8 @@ along with GCC; see the file COPYING3. If not see #include "sched-int.h" #include "sbitmap.h" #include "fibheap.h" +#include "tree-flow.h" +#include "tree-pass.h" enum upper_128bits_state { @@ -24443,6 +24445,28 @@ enum ix86_builtins /* CFString built-in for darwin */ IX86_BUILTIN_CFSTRING, + /* Builtins to get CPU features. */ + IX86_BUILTIN_CPU_SUPPORTS_CMOV, + IX86_BUILTIN_CPU_SUPPORTS_MMX, + IX86_BUILTIN_CPU_SUPPORTS_POPCOUNT, + IX86_BUILTIN_CPU_SUPPORTS_SSE, + IX86_BUILTIN_CPU_SUPPORTS_SSE2, + IX86_BUILTIN_CPU_SUPPORTS_SSE3, + IX86_BUILTIN_CPU_SUPPORTS_SSSE3, + IX86_BUILTIN_CPU_SUPPORTS_SSE4_1, + IX86_BUILTIN_CPU_SUPPORTS_SSE4_2, + /* Builtins to get CPU type. */ + IX86_BUILTIN_CPU_IS_AMD, + IX86_BUILTIN_CPU_IS_INTEL, + IX86_BUILTIN_CPU_IS_INTEL_ATOM, + IX86_BUILTIN_CPU_IS_INTEL_CORE2, + IX86_BUILTIN_CPU_IS_INTEL_COREI7_NEHALEM, + IX86_BUILTIN_CPU_IS_INTEL_COREI7_WESTMERE, + IX86_BUILTIN_CPU_IS_INTEL_COREI7_SANDYBRIDGE, + IX86_BUILTIN_CPU_IS_AMDFAM10_BARCELONA, + IX86_BUILTIN_CPU_IS_AMDFAM10_SHANGHAI, + IX86_BUILTIN_CPU_IS_AMDFAM10_ISTANBUL, + IX86_BUILTIN_MAX }; @@ -25809,6 +25833,316 @@ ix86_init_mmx_sse_builtins (void) } } +/* Returns a struct type with name NAME and number of fields equal to + NUM_FIELDS. Each field is a unsigned int bit field of length 1 bit. */ + +static tree +build_struct_with_one_bit_fields (int num_fields, const char *name) +{ + int i; + char field_name [10]; + tree field = NULL_TREE, field_chain = NULL_TREE; + tree type = make_node (RECORD_TYPE); + + strcpy (field_name, "k_field"); + + for (i = 0; i < num_fields; i++) + { + /* Name the fields, 0_field, 1_field, ... */ + field_name [0] = '0' + i; + field = build_decl (UNKNOWN_LOCATION, FIELD_DECL, + get_identifier (field_name), unsigned_type_node); + DECL_BIT_FIELD (field) = 1; + DECL_SIZE (field) = bitsize_one_node; + if (field_chain != NULL_TREE) + DECL_CHAIN (field) = field_chain; + field_chain = field; + } + finish_builtin_struct (type, name, field_chain, NULL_TREE); + return type; +} + +/* Returns a extern, comdat VAR_DECL of type TYPE and name NAME. */ + +static tree +make_var_decl (tree type, const char *name) +{ + tree new_decl; + struct varpool_node *vnode; + + new_decl = build_decl (UNKNOWN_LOCATION, + VAR_DECL, + get_identifier(name), + type); + + DECL_EXTERNAL (new_decl) = 1; + TREE_STATIC (new_decl) = 1; + TREE_PUBLIC (new_decl) = 1; + DECL_INITIAL (new_decl) = 0; + DECL_ARTIFICIAL (new_decl) = 0; + DECL_PRESERVE_P (new_decl) = 1; + + make_decl_one_only (new_decl, DECL_ASSEMBLER_NAME (new_decl)); + assemble_variable (new_decl, 0, 0, 0); + + vnode = varpool_node (new_decl); + gcc_assert (vnode != NULL); + /* Set finalized to 1, otherwise it asserts in function "write_symbol" in + lto-streamer-out.c. */ + vnode->finalized = 1; + + return new_decl; +} + +/* Traverses the chain of fields in STRUCT_TYPE and returns the FIELD_NUM + numbered field. */ + +static tree +get_field_from_struct (tree struct_type, int field_num) +{ + int i; + tree field = TYPE_FIELDS (struct_type); + + for (i = 0; i < field_num; i++, field = DECL_CHAIN(field)) + { + gcc_assert (field != NULL_TREE); + } + + return field; +} + +/* FNDECL is a __builtin_cpu_* call that is folded into an integer defined + in libgcc/config/i386/i386-cpuinfo.c */ + +static tree +fold_builtin_cpu (enum ix86_builtins fn_code) +{ + /* This is the order of bit-fields in __processor_features in + i386-cpuinfo.c */ + enum processor_features + { + F_CMOV = 0, + F_MMX, + F_POPCNT, + F_SSE, + F_SSE2, + F_SSE3, + F_SSSE3, + F_SSE4_1, + F_SSE4_2, + F_MAX + }; + + /* This is the order of bit-fields in __processor_model in + i386-cpuinfo.c */ + enum processor_model + { + M_AMD = 0, + M_INTEL, + M_INTEL_ATOM, + M_INTEL_CORE2, + M_INTEL_COREI7_NEHALEM, + M_INTEL_COREI7_WESTMERE, + M_INTEL_COREI7_SANDYBRIDGE, + M_AMDFAM10_BARCELONA, + M_AMDFAM10_SHANGHAI, + M_AMDFAM10_ISTANBUL, + M_MAX + }; + + static tree __processor_features_type = NULL_TREE; + static tree __cpu_features_var = NULL_TREE; + static tree __processor_model_type = NULL_TREE; + static tree __cpu_model_var = NULL_TREE; + static tree field; + static tree which_struct; + + if (__processor_features_type == NULL_TREE) + __processor_features_type = build_struct_with_one_bit_fields (F_MAX, + "__processor_features"); + + if (__processor_model_type == NULL_TREE) + __processor_model_type = build_struct_with_one_bit_fields (M_MAX, + "__processor_model"); + + if (__cpu_features_var == NULL_TREE) + __cpu_features_var = make_var_decl (__processor_features_type, + "__cpu_features"); + + if (__cpu_model_var == NULL_TREE) + __cpu_model_var = make_var_decl (__processor_model_type, + "__cpu_model"); + + /* Look at the code to identify the field requested. */ + switch (fn_code) + { + case IX86_BUILTIN_CPU_SUPPORTS_CMOV: + field = get_field_from_struct (__processor_features_type, F_CMOV); + which_struct = __cpu_features_var; + break; + case IX86_BUILTIN_CPU_SUPPORTS_MMX: + field = get_field_from_struct (__processor_features_type, F_MMX); + which_struct = __cpu_features_var; + break; + case IX86_BUILTIN_CPU_SUPPORTS_POPCOUNT: + field = get_field_from_struct (__processor_features_type, F_POPCNT); + which_struct = __cpu_features_var; + break; + case IX86_BUILTIN_CPU_SUPPORTS_SSE: + field = get_field_from_struct (__processor_features_type, F_SSE); + which_struct = __cpu_features_var; + break; + case IX86_BUILTIN_CPU_SUPPORTS_SSE2: + field = get_field_from_struct (__processor_features_type, F_SSE2); + which_struct = __cpu_features_var; + break; + case IX86_BUILTIN_CPU_SUPPORTS_SSE3: + field = get_field_from_struct (__processor_features_type, F_SSE3); + which_struct = __cpu_features_var; + break; + case IX86_BUILTIN_CPU_SUPPORTS_SSSE3: + field = get_field_from_struct (__processor_features_type, F_SSE3); + which_struct = __cpu_features_var; + break; + case IX86_BUILTIN_CPU_SUPPORTS_SSE4_1: + field = get_field_from_struct (__processor_features_type, F_SSE4_1); + which_struct = __cpu_features_var; + break; + case IX86_BUILTIN_CPU_SUPPORTS_SSE4_2: + field = get_field_from_struct (__processor_features_type, F_SSE4_2); + which_struct = __cpu_features_var; + break; + case IX86_BUILTIN_CPU_IS_AMD: + field = get_field_from_struct (__processor_model_type, M_AMD); + which_struct = __cpu_model_var; + break; + case IX86_BUILTIN_CPU_IS_INTEL: + field = get_field_from_struct (__processor_model_type, M_INTEL); + which_struct = __cpu_model_var; + break; + case IX86_BUILTIN_CPU_IS_INTEL_ATOM: + field = get_field_from_struct (__processor_model_type, M_INTEL_ATOM); + which_struct = __cpu_model_var; + break; + case IX86_BUILTIN_CPU_IS_INTEL_CORE2: + field = get_field_from_struct (__processor_model_type, M_INTEL_CORE2); + which_struct = __cpu_model_var; + break; + case IX86_BUILTIN_CPU_IS_INTEL_COREI7_NEHALEM: + field = get_field_from_struct (__processor_model_type, + M_INTEL_COREI7_NEHALEM); + which_struct = __cpu_model_var; + break; + case IX86_BUILTIN_CPU_IS_INTEL_COREI7_WESTMERE: + field = get_field_from_struct (__processor_model_type, + M_INTEL_COREI7_WESTMERE); + which_struct = __cpu_model_var; + break; + case IX86_BUILTIN_CPU_IS_INTEL_COREI7_SANDYBRIDGE: + field = get_field_from_struct (__processor_model_type, + M_INTEL_COREI7_SANDYBRIDGE); + which_struct = __cpu_model_var; + break; + case IX86_BUILTIN_CPU_IS_AMDFAM10_BARCELONA: + field = get_field_from_struct (__processor_model_type, + M_AMDFAM10_BARCELONA); + which_struct = __cpu_model_var; + break; + case IX86_BUILTIN_CPU_IS_AMDFAM10_SHANGHAI: + field = get_field_from_struct (__processor_model_type, + M_AMDFAM10_SHANGHAI); + which_struct = __cpu_model_var; + break; + case IX86_BUILTIN_CPU_IS_AMDFAM10_ISTANBUL: + field = get_field_from_struct (__processor_model_type, + M_AMDFAM10_ISTANBUL); + which_struct = __cpu_model_var; + break; + default: + return NULL_TREE; + } + + return build3 (COMPONENT_REF, TREE_TYPE (field), which_struct, field, NULL_TREE); +} + +static tree +ix86_fold_builtin (tree fndecl, int n_args ATTRIBUTE_UNUSED, + tree *args ATTRIBUTE_UNUSED, bool ignore ATTRIBUTE_UNUSED) +{ + const char* decl_name = IDENTIFIER_POINTER (DECL_NAME (fndecl)); + if (DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_MD + && strstr(decl_name, "__builtin_cpu") != NULL) + { + enum ix86_builtins code = (enum ix86_builtins) + DECL_FUNCTION_CODE (fndecl); + return fold_builtin_cpu (code); + } + return NULL_TREE; +} + +/* A builtin to return the cpu type or feature. Returns an integer + and is a const. */ + +static void +make_platform_builtin (const char* name, int code) +{ + tree decl; + tree type; + + type = ix86_get_builtin_func_type (INT_FTYPE_VOID); + decl = add_builtin_function (name, type, code, BUILT_IN_MD, + NULL, NULL_TREE); + gcc_assert (decl != NULL_TREE); + ix86_builtins[(int) code] = decl; + /* Mark this as a const function. */ + TREE_READONLY (decl) = 1; +} + +/* Builtins to get CPU type and features supported. */ + +static void +ix86_init_platform_type_builtins (void) +{ + make_platform_builtin ("__builtin_cpu_supports_cmov", + IX86_BUILTIN_CPU_SUPPORTS_CMOV); + make_platform_builtin ("__builtin_cpu_supports_mmx", + IX86_BUILTIN_CPU_SUPPORTS_MMX); + make_platform_builtin ("__builtin_cpu_supports_popcount", + IX86_BUILTIN_CPU_SUPPORTS_POPCOUNT); + make_platform_builtin ("__builtin_cpu_supports_sse", + IX86_BUILTIN_CPU_SUPPORTS_SSE); + make_platform_builtin ("__builtin_cpu_supports_sse2", + IX86_BUILTIN_CPU_SUPPORTS_SSE2); + make_platform_builtin ("__builtin_cpu_supports_sse3", + IX86_BUILTIN_CPU_SUPPORTS_SSE3); + make_platform_builtin ("__builtin_cpu_supports_ssse3", + IX86_BUILTIN_CPU_SUPPORTS_SSSE3); + make_platform_builtin ("__builtin_cpu_supports_sse4_1", + IX86_BUILTIN_CPU_SUPPORTS_SSE4_1); + make_platform_builtin ("__builtin_cpu_supports_sse4_2", + IX86_BUILTIN_CPU_SUPPORTS_SSE4_2); + make_platform_builtin ("__builtin_cpu_is_amd", + IX86_BUILTIN_CPU_IS_AMD); + make_platform_builtin ("__builtin_cpu_is_intel_atom", + IX86_BUILTIN_CPU_IS_INTEL_ATOM); + make_platform_builtin ("__builtin_cpu_is_intel_core2", + IX86_BUILTIN_CPU_IS_INTEL_CORE2); + make_platform_builtin ("__builtin_cpu_is_intel", + IX86_BUILTIN_CPU_IS_INTEL); + make_platform_builtin ("__builtin_cpu_is_intel_corei7_nehalem", + IX86_BUILTIN_CPU_IS_INTEL_COREI7_NEHALEM); + make_platform_builtin ("__builtin_cpu_is_intel_corei7_westmere", + IX86_BUILTIN_CPU_IS_INTEL_COREI7_WESTMERE); + make_platform_builtin ("__builtin_cpu_is_intel_corei7_sandybridge", + IX86_BUILTIN_CPU_IS_INTEL_COREI7_SANDYBRIDGE); + make_platform_builtin ("__builtin_cpu_is_amdfam10_barcelona", + IX86_BUILTIN_CPU_IS_AMDFAM10_BARCELONA); + make_platform_builtin ("__builtin_cpu_is_amdfam10_shanghai", + IX86_BUILTIN_CPU_IS_AMDFAM10_SHANGHAI); + make_platform_builtin ("__builtin_cpu_is_amdfam10_istanbul", + IX86_BUILTIN_CPU_IS_AMDFAM10_ISTANBUL); +} + /* Internal method for ix86_init_builtins. */ static void @@ -25892,6 +26226,9 @@ ix86_init_builtins (void) ix86_init_builtin_types (); + /* Builtins to get CPU type and features. */ + ix86_init_platform_type_builtins (); + /* TFmode support builtins. */ def_builtin_const (0, "__builtin_infq", FLOAT128_FTYPE_VOID, IX86_BUILTIN_INFQ); @@ -27351,6 +27688,35 @@ ix86_expand_builtin (tree exp, rtx target, rtx sub enum machine_mode mode0, mode1, mode2; unsigned int fcode = DECL_FUNCTION_CODE (fndecl); + /* For CPU builtins that can be folded, fold first and expand the fold. */ + switch (fcode) + { + case IX86_BUILTIN_CPU_SUPPORTS_CMOV: + case IX86_BUILTIN_CPU_SUPPORTS_MMX: + case IX86_BUILTIN_CPU_SUPPORTS_POPCOUNT: + case IX86_BUILTIN_CPU_SUPPORTS_SSE: + case IX86_BUILTIN_CPU_SUPPORTS_SSE2: + case IX86_BUILTIN_CPU_SUPPORTS_SSE3: + case IX86_BUILTIN_CPU_SUPPORTS_SSSE3: + case IX86_BUILTIN_CPU_SUPPORTS_SSE4_1: + case IX86_BUILTIN_CPU_SUPPORTS_SSE4_2: + case IX86_BUILTIN_CPU_IS_AMD: + case IX86_BUILTIN_CPU_IS_INTEL: + case IX86_BUILTIN_CPU_IS_INTEL_ATOM: + case IX86_BUILTIN_CPU_IS_INTEL_CORE2: + case IX86_BUILTIN_CPU_IS_INTEL_COREI7_NEHALEM: + case IX86_BUILTIN_CPU_IS_INTEL_COREI7_WESTMERE: + case IX86_BUILTIN_CPU_IS_INTEL_COREI7_SANDYBRIDGE: + case IX86_BUILTIN_CPU_IS_AMDFAM10_BARCELONA: + case IX86_BUILTIN_CPU_IS_AMDFAM10_SHANGHAI: + case IX86_BUILTIN_CPU_IS_AMDFAM10_ISTANBUL: + { + tree fold_expr = fold_builtin_cpu ((enum ix86_builtins) fcode); + gcc_assert (fold_expr != NULL_TREE); + return expand_expr (fold_expr, target, mode, EXPAND_NORMAL); + } + } + /* Determine whether the builtin function is available under the current ISA. Originally the builtin was not created if it wasn't applicable to the current ISA based on the command line switches. With function specific @@ -35097,6 +35463,9 @@ ix86_autovectorize_vector_sizes (void) #undef TARGET_BUILD_BUILTIN_VA_LIST #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list +#undef TARGET_FOLD_BUILTIN +#define TARGET_FOLD_BUILTIN ix86_fold_builtin + #undef TARGET_ENUM_VA_LIST_P #define TARGET_ENUM_VA_LIST_P ix86_enum_va_list