| Message ID | 20190616234744.8975-2-digetx@gmail.com |
|---|---|
| State | Deferred |
| Headers | show |
| Series | [v1,1/2] clocksource/drivers/tegra: Cycles can't be 0 | expand |
diff --git a/drivers/clocksource/timer-tegra.c b/drivers/clocksource/timer-tegra.c index 090c85358fe8..d0a46e10dbca 100644 --- a/drivers/clocksource/timer-tegra.c +++ b/drivers/clocksource/timer-tegra.c @@ -130,7 +130,7 @@ static int tegra_timer_setup(unsigned int cpu) clockevents_config_and_register(&to->clkevt, timer_of_rate(to), 1, /* min */ - 0x1fffffff); /* 29 bits */ + 0x20000000); /* 29 bits + 1 */ return 0; }
Tegra's timer has 29 bits for the counter. The counter's value is smaller than the actual value by 1, hence the maximum equals to 29 bits + 1. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> --- drivers/clocksource/timer-tegra.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)