diff mbox series

[v2] HE: Fix HE capability check for PPE threshold present

Message ID 20190612231007.6462-1-sven@narfation.org
State Accepted
Headers show
Series [v2] HE: Fix HE capability check for PPE threshold present | expand

Commit Message

Sven Eckelmann June 12, 2019, 11:10 p.m. UTC
From: Sven Eckelmann <seckelmann@datto.com>

The the mask for PPE threshold present in the HE phy capability byte 6 is
0x80 and not 0x6. This incorrect mask breaks the length calculation and as
result the acceptance of the HE capabilities for STAs which either:

* don't have the PPE threshold present bit set AND the Codebook Size={7,5}
  MU Feedback or the Triggered SU Beamforming feedback bit set

* do have the PPE threshold present set AND neither the Codebook Size={7,5}
  MU Feedback nor the Triggered SU Beamforming feedback bit set

Fixes: 8f5fc369e263 ("HE: Fix HE Capabilities element variable length encoding")
Signed-off-by: Sven Eckelmann <seckelmann@datto.com>
---
Cc: John Crispin <john@phrozen.org>
Cc: Shashidhar Lakkavalli <slakkavalli@datto.com>

v2:

- fix name of referenced bits of HE PHY cap byte 6 in commit message
---
 src/ap/ieee802_11_he.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

John Crispin June 17, 2019, 7:55 a.m. UTC | #1
On 13/06/2019 01:10, Sven Eckelmann wrote:
> From: Sven Eckelmann <seckelmann@datto.com>
>
> The the mask for PPE threshold present in the HE phy capability byte 6 is
> 0x80 and not 0x6. This incorrect mask breaks the length calculation and as
> result the acceptance of the HE capabilities for STAs which either:
>
> * don't have the PPE threshold present bit set AND the Codebook Size={7,5}
>    MU Feedback or the Triggered SU Beamforming feedback bit set
>
> * do have the PPE threshold present set AND neither the Codebook Size={7,5}
>    MU Feedback nor the Triggered SU Beamforming feedback bit set
>
> Fixes: 8f5fc369e263 ("HE: Fix HE Capabilities element variable length encoding")
> Signed-off-by: Sven Eckelmann <seckelmann@datto.com>
> ---
> Cc: John Crispin <john@phrozen.org>
> Cc: Shashidhar Lakkavalli <slakkavalli@datto.com>
>
> v2:
>
> - fix name of referenced bits of HE PHY cap byte 6 in commit message


Hi Sven,

thanks for the catch, I stumbled across this myself during my vacation 
while testing using hwsim.

     John


> ---
>   src/ap/ieee802_11_he.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/ap/ieee802_11_he.c b/src/ap/ieee802_11_he.c
> index ba22a174a..d3d3c1db3 100644
> --- a/src/ap/ieee802_11_he.c
> +++ b/src/ap/ieee802_11_he.c
> @@ -23,7 +23,7 @@ static u8 ieee80211_he_ppet_size(u8 ppe_thres_hdr, const u8 *phy_cap_info)
>   	u8 sz = 0, ru;
>   
>   	if ((phy_cap_info[HE_PHYCAP_PPE_THRESHOLD_PRESENT_IDX] &
> -	     HE_PHYCAP_PPE_THRESHOLD_PRESENT_IDX) == 0)
> +	     HE_PHYCAP_PPE_THRESHOLD_PRESENT) == 0)
>   		return 0;
>   
>   	ru = (ppe_thres_hdr >> HE_PPE_THRES_RU_INDEX_BITMASK_SHIFT) &
Jouni Malinen June 22, 2019, 8:01 p.m. UTC | #2
On Thu, Jun 13, 2019 at 01:10:07AM +0200, Sven Eckelmann wrote:
> The the mask for PPE threshold present in the HE phy capability byte 6 is
> 0x80 and not 0x6. This incorrect mask breaks the length calculation and as
> result the acceptance of the HE capabilities for STAs which either:
> 
> * don't have the PPE threshold present bit set AND the Codebook Size={7,5}
>   MU Feedback or the Triggered SU Beamforming feedback bit set
> 
> * do have the PPE threshold present set AND neither the Codebook Size={7,5}
>   MU Feedback nor the Triggered SU Beamforming feedback bit set

Thanks, applied.
diff mbox series

Patch

diff --git a/src/ap/ieee802_11_he.c b/src/ap/ieee802_11_he.c
index ba22a174a..d3d3c1db3 100644
--- a/src/ap/ieee802_11_he.c
+++ b/src/ap/ieee802_11_he.c
@@ -23,7 +23,7 @@  static u8 ieee80211_he_ppet_size(u8 ppe_thres_hdr, const u8 *phy_cap_info)
 	u8 sz = 0, ru;
 
 	if ((phy_cap_info[HE_PHYCAP_PPE_THRESHOLD_PRESENT_IDX] &
-	     HE_PHYCAP_PPE_THRESHOLD_PRESENT_IDX) == 0)
+	     HE_PHYCAP_PPE_THRESHOLD_PRESENT) == 0)
 		return 0;
 
 	ru = (ppe_thres_hdr >> HE_PPE_THRES_RU_INDEX_BITMASK_SHIFT) &