clk: tegra210: fix PLLU and PLLU_OUT1
diff mbox series

Message ID 20190612031434.10055-1-jckuo@nvidia.com
State New
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Series
  • clk: tegra210: fix PLLU and PLLU_OUT1
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Commit Message

JC Kuo June 12, 2019, 3:14 a.m. UTC
Full-speed and low-speed USB devices do not work with Tegra210
platforms because of incorrect PLLU/PLLU_OUT1 clock settings.

When full-speed device is connected:
[   14.059886] usb 1-3: new full-speed USB device number 2 using tegra-xusb
[   14.196295] usb 1-3: device descriptor read/64, error -71
[   14.436311] usb 1-3: device descriptor read/64, error -71
[   14.675749] usb 1-3: new full-speed USB device number 3 using tegra-xusb
[   14.812335] usb 1-3: device descriptor read/64, error -71
[   15.052316] usb 1-3: device descriptor read/64, error -71
[   15.164799] usb usb1-port3: attempt power cycle

When low-speed device is connected:
[   37.610949] usb usb1-port3: Cannot enable. Maybe the USB cable is bad?
[   38.557376] usb usb1-port3: Cannot enable. Maybe the USB cable is bad?
[   38.564977] usb usb1-port3: attempt power cycle

This commit fixes the issue by:
 1. initializing PLLU_OUT1 before initializing XUSB_FS_SRC clock
    because PLLU_OUT1 is parent of XUSB_FS_SRC.
 2. changing PLLU post-divider to /2 (DIVP=1) according to Technical
    Reference Manual.

Fixes: e745f992cf4b ("clk: tegra: Rework pll_u")
Signed-off-by: JC Kuo <jckuo@nvidia.com>
---
 drivers/clk/tegra/clk-tegra210.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

Comments

Peter De Schrijver June 13, 2019, 10:59 a.m. UTC | #1
On Wed, Jun 12, 2019 at 11:14:34AM +0800, JC Kuo wrote:
> Full-speed and low-speed USB devices do not work with Tegra210
> platforms because of incorrect PLLU/PLLU_OUT1 clock settings.
> 
> When full-speed device is connected:
> [   14.059886] usb 1-3: new full-speed USB device number 2 using tegra-xusb
> [   14.196295] usb 1-3: device descriptor read/64, error -71
> [   14.436311] usb 1-3: device descriptor read/64, error -71
> [   14.675749] usb 1-3: new full-speed USB device number 3 using tegra-xusb
> [   14.812335] usb 1-3: device descriptor read/64, error -71
> [   15.052316] usb 1-3: device descriptor read/64, error -71
> [   15.164799] usb usb1-port3: attempt power cycle
> 
> When low-speed device is connected:
> [   37.610949] usb usb1-port3: Cannot enable. Maybe the USB cable is bad?
> [   38.557376] usb usb1-port3: Cannot enable. Maybe the USB cable is bad?
> [   38.564977] usb usb1-port3: attempt power cycle
> 
> This commit fixes the issue by:
>  1. initializing PLLU_OUT1 before initializing XUSB_FS_SRC clock
>     because PLLU_OUT1 is parent of XUSB_FS_SRC.
>  2. changing PLLU post-divider to /2 (DIVP=1) according to Technical
>     Reference Manual.
> 
> Fixes: e745f992cf4b ("clk: tegra: Rework pll_u")
> Signed-off-by: JC Kuo <jckuo@nvidia.com>
> ---
>  drivers/clk/tegra/clk-tegra210.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 

Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Stephen Boyd June 25, 2019, 11:08 p.m. UTC | #2
Quoting JC Kuo (2019-06-11 20:14:34)
> Full-speed and low-speed USB devices do not work with Tegra210
> platforms because of incorrect PLLU/PLLU_OUT1 clock settings.
> 
> When full-speed device is connected:
> [   14.059886] usb 1-3: new full-speed USB device number 2 using tegra-xusb
> [   14.196295] usb 1-3: device descriptor read/64, error -71
> [   14.436311] usb 1-3: device descriptor read/64, error -71
> [   14.675749] usb 1-3: new full-speed USB device number 3 using tegra-xusb
> [   14.812335] usb 1-3: device descriptor read/64, error -71
> [   15.052316] usb 1-3: device descriptor read/64, error -71
> [   15.164799] usb usb1-port3: attempt power cycle
> 
> When low-speed device is connected:
> [   37.610949] usb usb1-port3: Cannot enable. Maybe the USB cable is bad?
> [   38.557376] usb usb1-port3: Cannot enable. Maybe the USB cable is bad?
> [   38.564977] usb usb1-port3: attempt power cycle
> 
> This commit fixes the issue by:
>  1. initializing PLLU_OUT1 before initializing XUSB_FS_SRC clock
>     because PLLU_OUT1 is parent of XUSB_FS_SRC.
>  2. changing PLLU post-divider to /2 (DIVP=1) according to Technical
>     Reference Manual.
> 
> Fixes: e745f992cf4b ("clk: tegra: Rework pll_u")
> Signed-off-by: JC Kuo <jckuo@nvidia.com>
> ---

Applied to clk-next

Patch
diff mbox series

diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index e1ba62d2b1a0..b3e070fb53f9 100644
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -2204,9 +2204,9 @@  static struct div_nmp pllu_nmp = {
 };
 
 static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
-	{ 12000000, 480000000, 40, 1, 0, 0 },
-	{ 13000000, 480000000, 36, 1, 0, 0 }, /* actual: 468.0 MHz */
-	{ 38400000, 480000000, 25, 2, 0, 0 },
+	{ 12000000, 480000000, 40, 1, 1, 0 },
+	{ 13000000, 480000000, 36, 1, 1, 0 }, /* actual: 468.0 MHz */
+	{ 38400000, 480000000, 25, 2, 1, 0 },
 	{        0,         0,  0, 0, 0, 0 },
 };
 
@@ -3333,6 +3333,7 @@  static struct tegra_clk_init_table init_table[] __initdata = {
 	{ TEGRA210_CLK_DFLL_REF, TEGRA210_CLK_PLL_P, 51000000, 1 },
 	{ TEGRA210_CLK_SBC4, TEGRA210_CLK_PLL_P, 12000000, 1 },
 	{ TEGRA210_CLK_PLL_RE_VCO, TEGRA210_CLK_CLK_MAX, 672000000, 1 },
+	{ TEGRA210_CLK_PLL_U_OUT1, TEGRA210_CLK_CLK_MAX, 48000000, 1 },
 	{ TEGRA210_CLK_XUSB_GATE, TEGRA210_CLK_CLK_MAX, 0, 1 },
 	{ TEGRA210_CLK_XUSB_SS_SRC, TEGRA210_CLK_PLL_U_480M, 120000000, 0 },
 	{ TEGRA210_CLK_XUSB_FS_SRC, TEGRA210_CLK_PLL_U_48M, 48000000, 0 },
@@ -3357,7 +3358,6 @@  static struct tegra_clk_init_table init_table[] __initdata = {
 	{ TEGRA210_CLK_PLL_DP, TEGRA210_CLK_CLK_MAX, 270000000, 0 },
 	{ TEGRA210_CLK_SOC_THERM, TEGRA210_CLK_PLL_P, 51000000, 0 },
 	{ TEGRA210_CLK_CCLK_G, TEGRA210_CLK_CLK_MAX, 0, 1 },
-	{ TEGRA210_CLK_PLL_U_OUT1, TEGRA210_CLK_CLK_MAX, 48000000, 1 },
 	{ TEGRA210_CLK_PLL_U_OUT2, TEGRA210_CLK_CLK_MAX, 60000000, 1 },
 	{ TEGRA210_CLK_SPDIF_IN_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
 	{ TEGRA210_CLK_I2S0_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },