diff mbox

[U-Boot,1/3] powerpc/mpc8xxx: Extend CWL table

Message ID 1314204027-9982-1-git-send-email-yorksun@freescale.com
State Accepted
Commit 2bba85f41246d2bc1db00f2b0cce831b5efd4dfe
Delegated to: Kumar Gala
Headers show

Commit Message

York Sun Aug. 24, 2011, 4:40 p.m. UTC 
Extend CAS write Latency (CWL) table to comply with DDR3 spec

Signed-off-by: York Sun <yorksun@freescale.com>
---
 arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c |   18 ++++++++++++++++--
 1 files changed, 16 insertions(+), 2 deletions(-)

Comments

Kumar Gala Sept. 2, 2011, 1:27 p.m. UTC | #1 
On Aug 24, 2011, at 11:40 AM, York Sun wrote:

> Extend CAS write Latency (CWL) table to comply with DDR3 spec
> 
> Signed-off-by: York Sun <yorksun@freescale.com>
> ---
> arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c |   18 ++++++++++++++++--
> 1 files changed, 16 insertions(+), 2 deletions(-)

applied to 85xx

- k
diff mbox

Patch

diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
index 391eb25..15cd375 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -96,6 +96,10 @@  static inline int fsl_ddr_get_rtt(void)
  *       6 if 2.5ns > tCK >= 1.875ns
  *       7 if 1.875ns > tCK >= 1.5ns
  *       8 if 1.5ns > tCK >= 1.25ns
+ *       9 if 1.25ns > tCK >= 1.07ns
+ *       10 if 1.07ns > tCK >= 0.935ns
+ *       11 if 0.935ns > tCK >= 0.833ns
+ *       12 if 0.833ns > tCK >= 0.75ns
  */
 static inline unsigned int compute_cas_write_latency(void)
 {
@@ -110,8 +114,18 @@  static inline unsigned int compute_cas_write_latency(void)
 		cwl = 7;
 	else if (mclk_ps >= 1250)
 		cwl = 8;
-	else
-		cwl = 8;
+	else if (mclk_ps >= 1070)
+		cwl = 9;
+	else if (mclk_ps >= 935)
+		cwl = 10;
+	else if (mclk_ps >= 833)
+		cwl = 11;
+	else if (mclk_ps >= 750)
+		cwl = 12;
+	else {
+		cwl = 12;
+		printf("Warning: CWL is out of range\n");
+	}
 	return cwl;
 }