From patchwork Tue Jun 11 10:51:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bitan Biswas X-Patchwork-Id: 1113673 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="Ol/pom0N"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45NRl01Tw9z9sDB for ; Tue, 11 Jun 2019 20:56:28 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388277AbfFKK4M (ORCPT ); Tue, 11 Jun 2019 06:56:12 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:6309 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727278AbfFKK4M (ORCPT ); Tue, 11 Jun 2019 06:56:12 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 11 Jun 2019 03:56:12 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 11 Jun 2019 03:56:11 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 11 Jun 2019 03:56:11 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 11 Jun 2019 10:51:41 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 11 Jun 2019 10:51:41 +0000 Received: from dhcp-10-19-65-14.client.nvidia.com (Not Verified[10.19.65.14]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 11 Jun 2019 03:51:41 -0700 From: Bitan Biswas To: Laxman Dewangan , Thierry Reding , Jonathan Hunter , , , , Peter Rosin , Wolfram Sang , Dmitry Osipenko CC: Shardar Mohammed , Sowjanya Komatineni , Mantravadi Karthik , Bitan Biswas Subject: [PATCH V5 7/7] i2c: tegra: remove BUG, BUG_ON Date: Tue, 11 Jun 2019 03:51:14 -0700 Message-ID: <1560250274-18499-7-git-send-email-bbiswas@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1560250274-18499-1-git-send-email-bbiswas@nvidia.com> References: <1560250274-18499-1-git-send-email-bbiswas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1560250572; bh=b7SaMPrZw/7m74Z5DtXk3AIZWNjZNWn00p4TGNxlq1I=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=Ol/pom0N9HoqFMTFoN0cJONyJxTEV+honSlFnOycPtF/lvURyZoIxo8vB32kd/6hN pYjBfP8fTPyw4cIe1MFyXFKehTl038C23cm3zROwKxWPXpmy3AmMDz7iQ3mRNH8EKY RRGk0hP/YHKie2psaibOj3ZcpNVi2+Q/O4iq2BOG+3Uob7VtqsDmZ8sDe1dRVEbaJN kvfwWKtMAH8w0SMAXotfWOAt9oftwKERisI8cP+csaZAKYjZtio9G7B01B6tm3ekUa HYRAp8Tu5ho5vvPKM+7NXBcou0L9cFkiFqyMxocENv0nR1yPF2c6MBLek7HdR/r8O1 Wu9hSu4qYDdQA== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Remove redundant BUG_ON calls or replace with WARN_ON_ONCE as needed. Remove BUG() and make Rx and Tx case handling similar. Add WARN_ON_ONCE check for non-zero rx_fifo_avail in tegra_i2c_empty_rx_fifo() and return new error I2C_ERR_UNEXPECTED_STATUS. Signed-off-by: Bitan Biswas --- drivers/i2c/busses/i2c-tegra.c | 25 +++++++++++++++++-------- 1 file changed, 17 insertions(+), 8 deletions(-) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 0596c12..2c8f051 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -73,6 +73,7 @@ #define I2C_ERR_NO_ACK BIT(0) #define I2C_ERR_ARBITRATION_LOST BIT(1) #define I2C_ERR_UNKNOWN_INTERRUPT BIT(2) +#define I2C_ERR_UNEXPECTED_STATUS BIT(3) #define PACKET_HEADER0_HEADER_SIZE_SHIFT 28 #define PACKET_HEADER0_PACKET_ID_SHIFT 16 @@ -516,15 +517,15 @@ static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev) */ if (rx_fifo_avail > 0 && (buf_remaining > 0 && buf_remaining < BYTES_PER_FIFO_WORD)) { - BUG_ON(buf_remaining > 3); val = i2c_readl(i2c_dev, I2C_RX_FIFO); val = cpu_to_le32(val); memcpy(buf, &val, buf_remaining); buf_remaining = 0; rx_fifo_avail--; } + if (WARN_ON_ONCE(rx_fifo_avail)) + return -EINVAL; - BUG_ON(rx_fifo_avail > 0 && buf_remaining > 0); i2c_dev->msg_buf_remaining = buf_remaining; i2c_dev->msg_buf = buf; @@ -582,7 +583,6 @@ static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev) */ if (tx_fifo_avail > 0 && (buf_remaining > 0 && buf_remaining < BYTES_PER_FIFO_WORD)) { - BUG_ON(buf_remaining > 3); memcpy(&val, buf, buf_remaining); val = le32_to_cpu(val); @@ -848,10 +848,16 @@ static irqreturn_t tegra_i2c_isr(int irq, void *dev_id) if (!i2c_dev->is_curr_dma_xfer) { if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) { - if (i2c_dev->msg_buf_remaining) - tegra_i2c_empty_rx_fifo(i2c_dev); - else - BUG(); + if (i2c_dev->msg_buf_remaining) { + if (tegra_i2c_empty_rx_fifo(i2c_dev)) { + i2c_dev->msg_err |= + I2C_ERR_UNEXPECTED_STATUS; + goto err; + } + } else { + tegra_i2c_mask_irq(i2c_dev, + I2C_INT_RX_FIFO_DATA_REQ); + } } if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) { @@ -877,7 +883,10 @@ static irqreturn_t tegra_i2c_isr(int irq, void *dev_id) if (status & I2C_INT_PACKET_XFER_COMPLETE) { if (i2c_dev->is_curr_dma_xfer) i2c_dev->msg_buf_remaining = 0; - BUG_ON(i2c_dev->msg_buf_remaining); + if (WARN_ON_ONCE(i2c_dev->msg_buf_remaining)) { + i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT; + goto err; + } complete(&i2c_dev->msg_complete); } goto done;