[V5,6/7] i2c: tegra: fix PIO rx/tx residual transfer check
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Message ID 1560250274-18499-6-git-send-email-bbiswas@nvidia.com
State New
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Series
  • [V5,1/7] i2c: tegra: clean up macros
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Commit Message

Bitan Biswas June 11, 2019, 10:51 a.m. UTC
Fix expression for residual bytes(less than word) transfer
in I2C PIO mode RX/TX.

Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
---
 drivers/i2c/busses/i2c-tegra.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

Comments

Wolfram Sang June 12, 2019, 10:24 a.m. UTC | #1
On Tue, Jun 11, 2019 at 03:51:13AM -0700, Bitan Biswas wrote:
> Fix expression for residual bytes(less than word) transfer
> in I2C PIO mode RX/TX.
> 
> Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>

I applied patches 1-5 to my for-next tree now. No need to resend them
anymore, you can focus on the remaining patches now.

Question: The nominal maintainer for this driver is

        Laxman Dewangan <ldewangan@nvidia.com> (supporter:TEGRA I2C DRIVER)

I wonder if he is still around and interested?

That aside, thanks a lot Dmitry for the review of this series!
Dmitry Osipenko June 12, 2019, 1:55 p.m. UTC | #2
11.06.2019 13:51, Bitan Biswas пишет:
> Fix expression for residual bytes(less than word) transfer
> in I2C PIO mode RX/TX.
> 
> Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
> ---
>  drivers/i2c/busses/i2c-tegra.c | 11 ++++++-----
>  1 file changed, 6 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
> index 4dfb4c1..0596c12 100644
> --- a/drivers/i2c/busses/i2c-tegra.c
> +++ b/drivers/i2c/busses/i2c-tegra.c
> @@ -514,7 +514,8 @@ static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
>  	 * If there is a partial word at the end of buf, handle it manually to
>  	 * prevent overwriting past the end of buf
>  	 */
> -	if (rx_fifo_avail > 0 && buf_remaining > 0) {
> +	if (rx_fifo_avail > 0 &&
> +	    (buf_remaining > 0 && buf_remaining < BYTES_PER_FIFO_WORD)) {

The buf_remaining >= BYTES_PER_FIFO_WORD is not possible to happen
because there are three possible cases:

1) buf_remaining > rx_fifo_avail * 4:

	In this case rx_fifo_avail = 0

2) buf_remaining < rx_fifo_avail * 4;

	In this case buf_remaining is always < 4 because
	words_to_transfer is a buf_remaining rounded down to 4
	and then divided by 4. Hence:

	buf_remaining -= (buf_remaining / 4) * 4 always results
	into buf_remaining < 4.

3) buf_remaining == rx_fifo_avail * 4:

	In this case rx_fifo_avail = 0 and buf_remaining = 0.

Case 2 should never happen and means that something gone wrong.

>  		BUG_ON(buf_remaining > 3);
>  		val = i2c_readl(i2c_dev, I2C_RX_FIFO);
>  		val = cpu_to_le32(val);
> @@ -557,11 +558,10 @@ static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
>  			words_to_transfer = tx_fifo_avail;
>  
>  		/*
> -		 * Update state before writing to FIFO.  If this casues us
> +		 * Update state before writing to FIFO.  If this causes us
>  		 * to finish writing all bytes (AKA buf_remaining goes to 0) we
>  		 * have a potential for an interrupt (PACKET_XFER_COMPLETE is
> -		 * not maskable).  We need to make sure that the isr sees
> -		 * buf_remaining as 0 and doesn't call us back re-entrantly.
> +		 * not maskable).
>  		 */
>  		buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
>  		tx_fifo_avail -= words_to_transfer;
> @@ -580,7 +580,8 @@ static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
>  	 * prevent reading past the end of buf, which could cross a page
>  	 * boundary and fault.
>  	 */
> -	if (tx_fifo_avail > 0 && buf_remaining > 0) {
> +	if (tx_fifo_avail > 0 &&
> +	    (buf_remaining > 0 && buf_remaining < BYTES_PER_FIFO_WORD)) {
>  		BUG_ON(buf_remaining > 3);
>  		memcpy(&val, buf, buf_remaining);
>  		val = le32_to_cpu(val);
> 

Same as for RX.
Dmitry Osipenko June 12, 2019, 2:30 p.m. UTC | #3
11.06.2019 13:51, Bitan Biswas пишет:
> Fix expression for residual bytes(less than word) transfer
> in I2C PIO mode RX/TX.
> 
> Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
> ---

[snip]

>  		/*
> -		 * Update state before writing to FIFO.  If this casues us
> +		 * Update state before writing to FIFO.  If this causes us
>  		 * to finish writing all bytes (AKA buf_remaining goes to 0) we
>  		 * have a potential for an interrupt (PACKET_XFER_COMPLETE is
> -		 * not maskable).  We need to make sure that the isr sees
> -		 * buf_remaining as 0 and doesn't call us back re-entrantly.
> +		 * not maskable).
>  		 */
>  		buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;

Looks like the comment could be removed altogether because it doesn't
make sense since interrupt handler is under xfer_lock which is kept
locked during of tegra_i2c_xfer_msg().

Moreover the comment says that "PACKET_XFER_COMPLETE is not maskable",
but then what I2C_INT_PACKET_XFER_COMPLETE masking does?
Bitan Biswas June 13, 2019, 9:59 a.m. UTC | #4
On 6/12/19 6:55 AM, Dmitry Osipenko wrote:
> 11.06.2019 13:51, Bitan Biswas пишет:
>> Fix expression for residual bytes(less than word) transfer
>> in I2C PIO mode RX/TX.
>>
>> Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
>> ---
>>   drivers/i2c/busses/i2c-tegra.c | 11 ++++++-----
>>   1 file changed, 6 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
>> index 4dfb4c1..0596c12 100644
>> --- a/drivers/i2c/busses/i2c-tegra.c
>> +++ b/drivers/i2c/busses/i2c-tegra.c
>> @@ -514,7 +514,8 @@ static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
>>   	 * If there is a partial word at the end of buf, handle it manually to
>>   	 * prevent overwriting past the end of buf
>>   	 */
>> -	if (rx_fifo_avail > 0 && buf_remaining > 0) {
>> +	if (rx_fifo_avail > 0 &&
>> +	    (buf_remaining > 0 && buf_remaining < BYTES_PER_FIFO_WORD)) {
> 
> The buf_remaining >= BYTES_PER_FIFO_WORD is not possible to happen
> because there are three possible cases:
> 
> 1) buf_remaining > rx_fifo_avail * 4:
> 
> 	In this case rx_fifo_avail = 0
> 
> 2) buf_remaining < rx_fifo_avail * 4;
> 
> 	In this case buf_remaining is always < 4 because
> 	words_to_transfer is a buf_remaining rounded down to 4
> 	and then divided by 4. Hence:
> 
> 	buf_remaining -= (buf_remaining / 4) * 4 always results
> 	into buf_remaining < 4.
> 
> 3) buf_remaining == rx_fifo_avail * 4:
> 
> 	In this case rx_fifo_avail = 0 and buf_remaining = 0.
> 
> Case 2 should never happen and means that something gone wrong.
> 
Yes I now agree with you. The first condition "rx_fifo_avail > 0" 
failure will take care and prevent need for additional checks.

>>   		BUG_ON(buf_remaining > 3);
>>   		val = i2c_readl(i2c_dev, I2C_RX_FIFO);
>>   		val = cpu_to_le32(val);
>> @@ -557,11 +558,10 @@ static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
>>   			words_to_transfer = tx_fifo_avail;
>>   
>>   		/*
>> -		 * Update state before writing to FIFO.  If this casues us
>> +		 * Update state before writing to FIFO.  If this causes us
>>   		 * to finish writing all bytes (AKA buf_remaining goes to 0) we
>>   		 * have a potential for an interrupt (PACKET_XFER_COMPLETE is
>> -		 * not maskable).  We need to make sure that the isr sees
>> -		 * buf_remaining as 0 and doesn't call us back re-entrantly.
>> +		 * not maskable).
>>   		 */
>>   		buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
>>   		tx_fifo_avail -= words_to_transfer;
>> @@ -580,7 +580,8 @@ static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
>>   	 * prevent reading past the end of buf, which could cross a page
>>   	 * boundary and fault.
>>   	 */
>> -	if (tx_fifo_avail > 0 && buf_remaining > 0) {
>> +	if (tx_fifo_avail > 0 &&
>> +	    (buf_remaining > 0 && buf_remaining < BYTES_PER_FIFO_WORD)) {
>>   		BUG_ON(buf_remaining > 3);
>>   		memcpy(&val, buf, buf_remaining);
>>   		val = le32_to_cpu(val);
>>
> 
> Same as for RX.
> 
Yes shall discard this patch from the next update.

-Thanks,
  Bitan
Bitan Biswas June 13, 2019, 11:30 a.m. UTC | #5
On 6/12/19 7:30 AM, Dmitry Osipenko wrote:
> 11.06.2019 13:51, Bitan Biswas пишет:
>> Fix expression for residual bytes(less than word) transfer
>> in I2C PIO mode RX/TX.
>>
>> Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
>> ---
> 
> [snip]
> 
>>   		/*
>> -		 * Update state before writing to FIFO.  If this casues us
>> +		 * Update state before writing to FIFO.  If this causes us
>>   		 * to finish writing all bytes (AKA buf_remaining goes to 0) we
>>   		 * have a potential for an interrupt (PACKET_XFER_COMPLETE is
>> -		 * not maskable).  We need to make sure that the isr sees
>> -		 * buf_remaining as 0 and doesn't call us back re-entrantly.
>> +		 * not maskable).
>>   		 */
>>   		buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
> 
> Looks like the comment could be removed altogether because it doesn't
> make sense since interrupt handler is under xfer_lock which is kept
> locked during of tegra_i2c_xfer_msg().
I would push a separate patch to remove this comment because of 
xfer_lock in ISR now.

> 
> Moreover the comment says that "PACKET_XFER_COMPLETE is not maskable",
> but then what I2C_INT_PACKET_XFER_COMPLETE masking does?
> 
I2C_INT_PACKET_XFER_COMPLETE masking support available in Tegra chips 
newer than Tegra30 allows one to not see interrupt after Packet transfer 
complete. With the xfer_lock in ISR the scenario discussed in comment 
can be ignored.

-regards,
  Bitan
Bitan Biswas June 13, 2019, 11:43 a.m. UTC | #6
On 6/12/19 3:24 AM, Wolfram Sang wrote:
> On Tue, Jun 11, 2019 at 03:51:13AM -0700, Bitan Biswas wrote:
>> Fix expression for residual bytes(less than word) transfer
>> in I2C PIO mode RX/TX.
>>
>> Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
> 
> I applied patches 1-5 to my for-next tree now. No need to resend them
> anymore, you can focus on the remaining patches now.
> 
> Question: The nominal maintainer for this driver is
> 
>          Laxman Dewangan <ldewangan@nvidia.com> (supporter:TEGRA I2C DRIVER)
> 
> I wonder if he is still around and interested?
> 
> That aside, thanks a lot Dmitry for the review of this series!
> 
Thanks Wolfram. I shall work on remaining patches.
Laxman Dewangan June 13, 2019, 11:52 a.m. UTC | #7
On Wednesday 12 June 2019 03:54 PM, Wolfram Sang wrote:
> On Tue, Jun 11, 2019 at 03:51:13AM -0700, Bitan Biswas wrote:
>> Fix expression for residual bytes(less than word) transfer
>> in I2C PIO mode RX/TX.
>>
>> Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
> I applied patches 1-5 to my for-next tree now. No need to resend them
> anymore, you can focus on the remaining patches now.
>
> Question: The nominal maintainer for this driver is
>
>          Laxman Dewangan <ldewangan@nvidia.com> (supporter:TEGRA I2C DRIVER)
>
> I wonder if he is still around and interested?
>
> That aside, thanks a lot Dmitry for the review of this series!
>
Most of patches are coming from the downstream as part of upstream 
effort. Hence not reviewing explicitly.
Dmitry Osipenko June 13, 2019, 12:28 p.m. UTC | #8
13.06.2019 14:30, Bitan Biswas пишет:
> 
> 
> On 6/12/19 7:30 AM, Dmitry Osipenko wrote:
>> 11.06.2019 13:51, Bitan Biswas пишет:
>>> Fix expression for residual bytes(less than word) transfer
>>> in I2C PIO mode RX/TX.
>>>
>>> Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
>>> ---
>>
>> [snip]
>>
>>>           /*
>>> -         * Update state before writing to FIFO.  If this casues us
>>> +         * Update state before writing to FIFO.  If this causes us
>>>            * to finish writing all bytes (AKA buf_remaining goes to
>>> 0) we
>>>            * have a potential for an interrupt (PACKET_XFER_COMPLETE is
>>> -         * not maskable).  We need to make sure that the isr sees
>>> -         * buf_remaining as 0 and doesn't call us back re-entrantly.
>>> +         * not maskable).
>>>            */
>>>           buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
>>
>> Looks like the comment could be removed altogether because it doesn't
>> make sense since interrupt handler is under xfer_lock which is kept
>> locked during of tegra_i2c_xfer_msg().
> I would push a separate patch to remove this comment because of
> xfer_lock in ISR now.
> 
>>
>> Moreover the comment says that "PACKET_XFER_COMPLETE is not maskable",
>> but then what I2C_INT_PACKET_XFER_COMPLETE masking does?
>>
> I2C_INT_PACKET_XFER_COMPLETE masking support available in Tegra chips
> newer than Tegra30 allows one to not see interrupt after Packet transfer
> complete. With the xfer_lock in ISR the scenario discussed in comment
> can be ignored.

Also note that xfer_lock could be removed and replaced with a just
irq_enable/disable() calls in tegra_i2c_xfer_msg() because we only care
about IRQ not firing during of the preparation process.

It also looks like tegra_i2c_[un]nmask_irq isn't really needed and all
IRQ's could be simply unmasked during the driver's probe, in that case
it may worth to add a kind of "in-progress" flag to catch erroneous
interrupts.
Wolfram Sang June 13, 2019, 1:13 p.m. UTC | #9
> Most of patches are coming from the downstream as part of upstream effort.
> Hence not reviewing explicitly.

It would help me a lot if you could ack the patches, then, once you are
fine with them. I am really relying on driver maintainers these days. An
ack or rev from them is kinda required and speeds up things
significantly.
Bitan Biswas June 14, 2019, 9:50 a.m. UTC | #10
On 6/13/19 5:28 AM, Dmitry Osipenko wrote:
> 13.06.2019 14:30, Bitan Biswas пишет:
>>
>>
>> On 6/12/19 7:30 AM, Dmitry Osipenko wrote:
>>> 11.06.2019 13:51, Bitan Biswas пишет:
>>>> Fix expression for residual bytes(less than word) transfer
>>>> in I2C PIO mode RX/TX.
>>>>
>>>> Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
>>>> ---
>>>
>>> [snip]
>>>
>>>>            /*
>>>> -         * Update state before writing to FIFO.  If this casues us
>>>> +         * Update state before writing to FIFO.  If this causes us
>>>>             * to finish writing all bytes (AKA buf_remaining goes to
>>>> 0) we
>>>>             * have a potential for an interrupt (PACKET_XFER_COMPLETE is
>>>> -         * not maskable).  We need to make sure that the isr sees
>>>> -         * buf_remaining as 0 and doesn't call us back re-entrantly.
>>>> +         * not maskable).
>>>>             */
>>>>            buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
>>>
>>> Looks like the comment could be removed altogether because it doesn't
>>> make sense since interrupt handler is under xfer_lock which is kept
>>> locked during of tegra_i2c_xfer_msg().
>> I would push a separate patch to remove this comment because of
>> xfer_lock in ISR now.
>>
>>>
>>> Moreover the comment says that "PACKET_XFER_COMPLETE is not maskable",
>>> but then what I2C_INT_PACKET_XFER_COMPLETE masking does?
>>>
>> I2C_INT_PACKET_XFER_COMPLETE masking support available in Tegra chips
>> newer than Tegra30 allows one to not see interrupt after Packet transfer
>> complete. With the xfer_lock in ISR the scenario discussed in comment
>> can be ignored.
> 
> Also note that xfer_lock could be removed and replaced with a just
> irq_enable/disable() calls in tegra_i2c_xfer_msg() because we only care
> about IRQ not firing during of the preparation process.
This should need sufficient testing hence let us do it in a different 
series.

> 
> It also looks like tegra_i2c_[un]nmask_irq isn't really needed and all
> IRQ's could be simply unmasked during the driver's probe, in that case
> it may worth to add a kind of "in-progress" flag to catch erroneous
> interrupts.
> 
TX interrupt needs special handling if this change is done. Hence I 
think it should be taken up after sufficient testing in a separate patch.

-regards,
  Bitan
Dmitry Osipenko June 14, 2019, 1:02 p.m. UTC | #11
14.06.2019 12:50, Bitan Biswas пишет:
> 
> 
> On 6/13/19 5:28 AM, Dmitry Osipenko wrote:
>> 13.06.2019 14:30, Bitan Biswas пишет:
>>>
>>>
>>> On 6/12/19 7:30 AM, Dmitry Osipenko wrote:
>>>> 11.06.2019 13:51, Bitan Biswas пишет:
>>>>> Fix expression for residual bytes(less than word) transfer
>>>>> in I2C PIO mode RX/TX.
>>>>>
>>>>> Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
>>>>> ---
>>>>
>>>> [snip]
>>>>
>>>>>            /*
>>>>> -         * Update state before writing to FIFO.  If this casues us
>>>>> +         * Update state before writing to FIFO.  If this causes us
>>>>>             * to finish writing all bytes (AKA buf_remaining goes to
>>>>> 0) we
>>>>>             * have a potential for an interrupt (PACKET_XFER_COMPLETE is
>>>>> -         * not maskable).  We need to make sure that the isr sees
>>>>> -         * buf_remaining as 0 and doesn't call us back re-entrantly.
>>>>> +         * not maskable).
>>>>>             */
>>>>>            buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
>>>>
>>>> Looks like the comment could be removed altogether because it doesn't
>>>> make sense since interrupt handler is under xfer_lock which is kept
>>>> locked during of tegra_i2c_xfer_msg().
>>> I would push a separate patch to remove this comment because of
>>> xfer_lock in ISR now.
>>>
>>>>
>>>> Moreover the comment says that "PACKET_XFER_COMPLETE is not maskable",
>>>> but then what I2C_INT_PACKET_XFER_COMPLETE masking does?
>>>>
>>> I2C_INT_PACKET_XFER_COMPLETE masking support available in Tegra chips
>>> newer than Tegra30 allows one to not see interrupt after Packet transfer
>>> complete. With the xfer_lock in ISR the scenario discussed in comment
>>> can be ignored.
>>
>> Also note that xfer_lock could be removed and replaced with a just
>> irq_enable/disable() calls in tegra_i2c_xfer_msg() because we only care
>> about IRQ not firing during of the preparation process.
> This should need sufficient testing hence let us do it in a different series.

I don't think that there is much to test here since obviously it should work.

>>
>> It also looks like tegra_i2c_[un]nmask_irq isn't really needed and all
>> IRQ's could be simply unmasked during the driver's probe, in that case
>> it may worth to add a kind of "in-progress" flag to catch erroneous
>> interrupts.
>>
> TX interrupt needs special handling if this change is done. Hence I think it should be
> taken up after sufficient testing in a separate patch.

This one is indeed a bit more trickier. Probably another alternative could be to keep GIC
interrupt disabled while no transfer is performed, then you'll have to request interrupt
in a disabled state using IRQ_NOAUTOEN flag.

And yes, that all should be a separate changes if you're going to implement them.
Bitan Biswas June 18, 2019, 5:21 a.m. UTC | #12
On 6/14/19 6:02 AM, Dmitry Osipenko wrote:
> 14.06.2019 12:50, Bitan Biswas пишет:
>>
>>
>> On 6/13/19 5:28 AM, Dmitry Osipenko wrote:
>>> 13.06.2019 14:30, Bitan Biswas пишет:
>>>>
>>>>
>>>> On 6/12/19 7:30 AM, Dmitry Osipenko wrote:
>>>>> 11.06.2019 13:51, Bitan Biswas пишет:
>>>>>> Fix expression for residual bytes(less than word) transfer
>>>>>> in I2C PIO mode RX/TX.
>>>>>>
>>>>>> Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
>>>>>> ---
>>>>>
>>>>> [snip]
>>>>>
>>>>>>             /*
>>>>>> -         * Update state before writing to FIFO.  If this casues us
>>>>>> +         * Update state before writing to FIFO.  If this causes us
>>>>>>              * to finish writing all bytes (AKA buf_remaining goes to
>>>>>> 0) we
>>>>>>              * have a potential for an interrupt (PACKET_XFER_COMPLETE is
>>>>>> -         * not maskable).  We need to make sure that the isr sees
>>>>>> -         * buf_remaining as 0 and doesn't call us back re-entrantly.
>>>>>> +         * not maskable).
>>>>>>              */
>>>>>>             buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
>>>>>
>>>>> Looks like the comment could be removed altogether because it doesn't
>>>>> make sense since interrupt handler is under xfer_lock which is kept
>>>>> locked during of tegra_i2c_xfer_msg().
>>>> I would push a separate patch to remove this comment because of
>>>> xfer_lock in ISR now.
>>>>
>>>>>
>>>>> Moreover the comment says that "PACKET_XFER_COMPLETE is not maskable",
>>>>> but then what I2C_INT_PACKET_XFER_COMPLETE masking does?
>>>>>
>>>> I2C_INT_PACKET_XFER_COMPLETE masking support available in Tegra chips
>>>> newer than Tegra30 allows one to not see interrupt after Packet transfer
>>>> complete. With the xfer_lock in ISR the scenario discussed in comment
>>>> can be ignored.
>>>
>>> Also note that xfer_lock could be removed and replaced with a just
>>> irq_enable/disable() calls in tegra_i2c_xfer_msg() because we only care
>>> about IRQ not firing during of the preparation process.
>> This should need sufficient testing hence let us do it in a different series.
> 
> I don't think that there is much to test here since obviously it should work.
> 
I shall push a patch for this as basic i2c read write test passed.

>>>
>>> It also looks like tegra_i2c_[un]nmask_irq isn't really needed and all
>>> IRQ's could be simply unmasked during the driver's probe, in that case
>>> it may worth to add a kind of "in-progress" flag to catch erroneous
>>> interrupts.
>>>
>> TX interrupt needs special handling if this change is done. Hence I think it should be
>> taken up after sufficient testing in a separate patch.
> 
> This one is indeed a bit more trickier. Probably another alternative could be to keep GIC
> interrupt disabled while no transfer is performed, then you'll have to request interrupt
> in a disabled state using IRQ_NOAUTOEN flag.
> 
> And yes, that all should be a separate changes if you're going to implement them.
> 
OK

-Thanks,
  Bitan

Patch
diff mbox series

diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
index 4dfb4c1..0596c12 100644
--- a/drivers/i2c/busses/i2c-tegra.c
+++ b/drivers/i2c/busses/i2c-tegra.c
@@ -514,7 +514,8 @@  static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
 	 * If there is a partial word at the end of buf, handle it manually to
 	 * prevent overwriting past the end of buf
 	 */
-	if (rx_fifo_avail > 0 && buf_remaining > 0) {
+	if (rx_fifo_avail > 0 &&
+	    (buf_remaining > 0 && buf_remaining < BYTES_PER_FIFO_WORD)) {
 		BUG_ON(buf_remaining > 3);
 		val = i2c_readl(i2c_dev, I2C_RX_FIFO);
 		val = cpu_to_le32(val);
@@ -557,11 +558,10 @@  static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
 			words_to_transfer = tx_fifo_avail;
 
 		/*
-		 * Update state before writing to FIFO.  If this casues us
+		 * Update state before writing to FIFO.  If this causes us
 		 * to finish writing all bytes (AKA buf_remaining goes to 0) we
 		 * have a potential for an interrupt (PACKET_XFER_COMPLETE is
-		 * not maskable).  We need to make sure that the isr sees
-		 * buf_remaining as 0 and doesn't call us back re-entrantly.
+		 * not maskable).
 		 */
 		buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
 		tx_fifo_avail -= words_to_transfer;
@@ -580,7 +580,8 @@  static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
 	 * prevent reading past the end of buf, which could cross a page
 	 * boundary and fault.
 	 */
-	if (tx_fifo_avail > 0 && buf_remaining > 0) {
+	if (tx_fifo_avail > 0 &&
+	    (buf_remaining > 0 && buf_remaining < BYTES_PER_FIFO_WORD)) {
 		BUG_ON(buf_remaining > 3);
 		memcpy(&val, buf, buf_remaining);
 		val = le32_to_cpu(val);