From patchwork Wed Aug 24 05:04:36 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Liu X-Patchwork-Id: 111241 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Received: from merlin.infradead.org (merlin.infradead.org [IPv6:2001:4978:20e::2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 480B0B6F71 for ; Wed, 24 Aug 2011 15:00:31 +1000 (EST) Received: from canuck.infradead.org ([2001:4978:20e::1]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1Qw5ZX-0007Uf-S1; Wed, 24 Aug 2011 05:00:19 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1Qw5ZX-0001WU-2T; Wed, 24 Aug 2011 05:00:15 +0000 Received: from ch1ehsobe001.messaging.microsoft.com ([216.32.181.181] helo=ch1outboundpool.messaging.microsoft.com) by canuck.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1Qw5Yy-0001QA-5F for linux-arm-kernel@lists.infradead.org; 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Wed, 24 Aug 2011 04:59:35 +0000 Received: from az33smr01.freescale.net (10.64.34.199) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server id 14.1.323.2; Tue, 23 Aug 2011 23:59:34 -0500 Received: from r64343-desktop.ap.freescale.net (r64343-desktop.ap.freescale.net [10.192.242.36]) by az33smr01.freescale.net (8.13.1/8.13.0) with ESMTP id p7O4xOaC004658; Tue, 23 Aug 2011 23:59:33 -0500 (CDT) From: Jason Liu To: Subject: [[PATCH v2 5/6] ARM: mx35: use generic function for displaying silicon revision Date: Wed, 24 Aug 2011 13:04:36 +0800 Message-ID: <1314162277-2840-6-git-send-email-jason.hui@linaro.org> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1314162277-2840-1-git-send-email-jason.hui@linaro.org> References: <1314162277-2840-1-git-send-email-jason.hui@linaro.org> MIME-Version: 1.0 X-OriginatorOrg: sigmatel.com X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110824_005940_459794_1BA6F0C0 X-CRM114-Status: GOOD ( 12.80 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [216.32.181.181 listed in list.dnswl.org] Cc: s.hauer@pengutronix.de, patches@linaro.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org update to use generic function for displaying silicon revision Signed-off-by: Jason Liu Cc: Fabio Estevam Cc: Sascha Hauer --- arch/arm/mach-imx/clock-imx35.c | 3 ++- arch/arm/mach-imx/cpu-imx35.c | 30 ++++++++++++++---------------- arch/arm/plat-mxc/include/mach/mx3x.h | 9 +-------- 3 files changed, 17 insertions(+), 25 deletions(-) diff --git a/arch/arm/mach-imx/clock-imx35.c b/arch/arm/mach-imx/clock-imx35.c index 88b62a0..abf30d4 100644 --- a/arch/arm/mach-imx/clock-imx35.c +++ b/arch/arm/mach-imx/clock-imx35.c @@ -537,7 +537,8 @@ int __init mx35_clocks_init() __raw_writel(cgr3, CCM_BASE + CCM_CGR3); clk_enable(&iim_clk); - mx35_read_cpu_rev(); + imx_print_silicon_rev("i.MX35", mx35_revision()); + clk_disable(&iim_clk); #ifdef CONFIG_MXC_USE_EPIT epit_timer_init(&epit1_clk, diff --git a/arch/arm/mach-imx/cpu-imx35.c b/arch/arm/mach-imx/cpu-imx35.c index 6637cd8..846e46e 100644 --- a/arch/arm/mach-imx/cpu-imx35.c +++ b/arch/arm/mach-imx/cpu-imx35.c @@ -13,32 +13,30 @@ #include #include -unsigned int mx35_cpu_rev; -EXPORT_SYMBOL(mx35_cpu_rev); +static int mx35_cpu_rev = -1; -void __init mx35_read_cpu_rev(void) +static int mx35_read_cpu_rev(void) { u32 rev; - char *srev; rev = __raw_readl(MX35_IO_ADDRESS(MX35_IIM_BASE_ADDR + MXC_IIMSREV)); switch (rev) { case 0x00: - mx35_cpu_rev = IMX_CHIP_REVISION_1_0; - srev = "1.0"; - break; + return IMX_CHIP_REVISION_1_0; case 0x10: - mx35_cpu_rev = IMX_CHIP_REVISION_2_0; - srev = "2.0"; - break; + return IMX_CHIP_REVISION_2_0; case 0x11: - mx35_cpu_rev = IMX_CHIP_REVISION_2_1; - srev = "2.1"; - break; + return IMX_CHIP_REVISION_2_1; default: - mx35_cpu_rev = IMX_CHIP_REVISION_UNKNOWN; - srev = "unknown"; + return IMX_CHIP_REVISION_UNKNOWN; } +} + +int mx35_revision(void) +{ + if (mx35_cpu_rev == -1) + mx35_cpu_rev = mx35_read_cpu_rev(); - printk(KERN_INFO "CPU identified as i.MX35, silicon rev %s\n", srev); + return mx35_cpu_rev; } +EXPORT_SYMBOL(mx35_revision); diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h index e1850f4..30dbf42 100644 --- a/arch/arm/plat-mxc/include/mach/mx3x.h +++ b/arch/arm/plat-mxc/include/mach/mx3x.h @@ -187,14 +187,7 @@ /* Mandatory defines used globally */ #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) -extern unsigned int mx35_cpu_rev; -extern void mx35_read_cpu_rev(void); - -static inline int mx35_revision(void) -{ - return mx35_cpu_rev; -} - +extern int mx35_revision(void); extern int mx31_revision(void); #endif