From patchwork Fri Jun 7 14:46:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 1111938 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="kyXj4LM4"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45L54w1k26z9sNm for ; Sat, 8 Jun 2019 00:48:48 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729720AbfFGOsn (ORCPT ); Fri, 7 Jun 2019 10:48:43 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:19407 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728724AbfFGOsn (ORCPT ); Fri, 7 Jun 2019 10:48:43 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 07 Jun 2019 07:48:26 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Fri, 07 Jun 2019 07:48:42 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Fri, 07 Jun 2019 07:48:42 -0700 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 7 Jun 2019 14:48:41 +0000 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 7 Jun 2019 14:48:41 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Fri, 7 Jun 2019 14:48:41 +0000 Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.37.38]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Fri, 07 Jun 2019 07:48:41 -0700 From: Vidya Sagar To: , , , , , , , , , , CC: , , , , , , , , , , Subject: [PATCH V9 10/15] dt-bindings: PHY: P2U: Add Tegra194 P2U block Date: Fri, 7 Jun 2019 20:16:35 +0530 Message-ID: <20190607144640.13427-11-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190607144640.13427-1-vidyas@nvidia.com> References: <20190607144640.13427-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1559918907; bh=iyS9BBtV4ePiAAhBp8YPZYnjkVFJ4s2xySkGdXu3dA0=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=kyXj4LM4nm1MHyvkgco+XcBzDqMSPxYi9bZTX3STA0kz9vbf3z5yo9CMmooiofVCH YKOriOQFUWGpY6QS0V7tQv3M6T/QIADU0g7x8Bzrl+1jI2vYYjZb0Pq9smdabOL+P7 29W/PNh6jDGjr+o+4Es4pfr60TXE+D+HMyvPZa7wM90EKq5REx9yREYdR16hYURbQi riv0spKCOscPAJpJ+KtE0rQwp28v0AScEE/eZTmbTd6Q5xHo2PNXrdG78B3TkfRDDf RUtsIlAEoab02Sb1SWKDY4rM5NnHYcIn/tpubA8xaWlj+TOAq/SC2a8rwkCbFRwF9l 8szQtrXL/QGeQ== Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support for Tegra194 P2U (PIPE to UPHY) module block which is a glue module instantiated one for each PCIe lane between Synopsys DesignWare core based PCIe IP and Universal PHY block. Signed-off-by: Vidya Sagar Reviewed-by: Rob Herring Acked-by: Thierry Reding --- Changes since [v8]: * None Changes since [v7]: * None Changes since [v6]: * None Changes since [v5]: * Added Sob * Changed node name from "p2u@xxxxxxxx" to "phy@xxxxxxxx" Changes since [v4]: * None Changes since [v3]: * None Changes since [v2]: * Changed node label to reflect new format that includes either 'hsio' or 'nvhs' in its name to reflect which UPHY brick they belong to Changes since [v1]: * This is a new patch in v2 series .../bindings/phy/phy-tegra194-p2u.txt | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/phy-tegra194-p2u.txt diff --git a/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.txt b/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.txt new file mode 100644 index 000000000000..d23ff90baad5 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.txt @@ -0,0 +1,28 @@ +NVIDIA Tegra194 P2U binding + +Tegra194 has two PHY bricks namely HSIO (High Speed IO) and NVHS (NVIDIA High +Speed) each interfacing with 12 and 8 P2U instances respectively. +A P2U instance is a glue logic between Synopsys DesignWare Core PCIe IP's PIPE +interface and PHY of HSIO/NVHS bricks. Each P2U instance represents one PCIe +lane. + +Required properties: +- compatible: For Tegra19x, must contain "nvidia,tegra194-p2u". +- reg: Should be the physical address space and length of respective each P2U + instance. +- reg-names: Must include the entry "ctl". + +Required properties for PHY port node: +- #phy-cells: Defined by generic PHY bindings. Must be 0. + +Refer to phy/phy-bindings.txt for the generic PHY binding properties. + +Example: + +p2u_hsio_0: phy@3e10000 { + compatible = "nvidia,tegra194-p2u"; + reg = <0x03e10000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; +};