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[PULL,v2,07/34] s390x: Align vector registers to 16 bytes

Message ID 20190607141727.29018-8-cohuck@redhat.com
State New
Headers show
Series [PULL,v2,01/34] MAINTAINERS: cover tests/migration/s390x/ | expand

Commit Message

Cornelia Huck June 7, 2019, 2:17 p.m. UTC 
From: David Hildenbrand <david@redhat.com>

11e2bfef7990 ("tcg/i386: Use MOVDQA for TCG_TYPE_V128 load/store")
revealed that the vregs are not aligned to 16 bytes. Align them to
16 bytes, to avoid segfault'ing on x86.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
 target/s390x/cpu.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
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Patch

diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index 7305cacc7b77..1bed12b6c3e0 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -66,7 +66,7 @@  struct CPUS390XState {
      * The floating point registers are part of the vector registers.
      * vregs[0][0] -> vregs[15][0] are 16 floating point registers
      */
-    CPU_DoubleU vregs[32][2];  /* vector registers */
+    CPU_DoubleU vregs[32][2] QEMU_ALIGNED(16);  /* vector registers */
     uint32_t aregs[16];    /* access registers */
     uint8_t riccb[64];     /* runtime instrumentation control */
     uint64_t gscb[4];      /* guarded storage control */