From patchwork Tue Aug 23 13:07:44 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Liu X-Patchwork-Id: 111094 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Received: from merlin.infradead.org (merlin.infradead.org [IPv6:2001:4978:20e::2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id D9D09B6FD7 for ; Tue, 23 Aug 2011 23:05:14 +1000 (EST) Received: from canuck.infradead.org ([2001:4978:20e::1]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1Qvqf0-0001My-1D; Tue, 23 Aug 2011 13:04:54 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1Qvqey-0001H3-Or; Tue, 23 Aug 2011 13:04:52 +0000 Received: from db3ehsobe001.messaging.microsoft.com ([213.199.154.139] helo=DB3EHSOBE001.bigfish.com) by canuck.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QvqeS-00019X-QH for linux-arm-kernel@lists.infradead.org; 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Tue, 23 Aug 2011 13:02:46 +0000 Received: from az33smr01.freescale.net (10.64.34.199) by 039-SN1MMR1-003.039d.mgd.msft.net (10.84.1.16) with Microsoft SMTP Server id 14.1.323.2; Tue, 23 Aug 2011 08:02:44 -0500 Received: from r64343-desktop.ap.freescale.net (r64343-desktop.ap.freescale.net [10.192.242.36]) by az33smr01.freescale.net (8.13.1/8.13.0) with ESMTP id p7ND2Wd7022085; Tue, 23 Aug 2011 08:02:42 -0500 (CDT) From: Jason Liu To: Subject: [PATCH 6/6] ARM: mx5: use generic function for displaying silicon revision Date: Tue, 23 Aug 2011 21:07:44 +0800 Message-ID: <1314104864-3725-7-git-send-email-jason.hui@linaro.org> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1314104864-3725-1-git-send-email-jason.hui@linaro.org> References: <1314104864-3725-1-git-send-email-jason.hui@linaro.org> MIME-Version: 1.0 X-OriginatorOrg: sigmatel.com X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110823_090421_181028_D8A0C34A X-CRM114-Status: GOOD ( 16.99 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [213.199.154.139 listed in list.dnswl.org] Cc: s.hauer@pengutronix.de, patches@linaro.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org Update to use generic function for displaying silicon revision Signed-off-by: Jason Liu Cc: Fabio Estevam Cc: Sascha Hauer --- arch/arm/mach-mx5/clock-mx51-mx53.c | 6 +-- arch/arm/mach-mx5/cpu.c | 74 ++++++++--------------------------- 2 files changed, 19 insertions(+), 61 deletions(-) diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c index f7bf996..0e23e1d 100644 --- a/arch/arm/mach-mx5/clock-mx51-mx53.c +++ b/arch/arm/mach-mx5/clock-mx51-mx53.c @@ -1548,9 +1548,8 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, clk_enable(&main_bus_clk); clk_enable(&iim_clk); - mx51_revision(); + imx_print_silicon_rev("i.MX51", mx51_revision()); clk_disable(&iim_clk); - mx51_display_revision(); /* move usb_phy_clk to 24MHz */ clk_set_parent(&usb_phy1_clk, &osc_clk); @@ -1592,9 +1591,8 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc, clk_enable(&main_bus_clk); clk_enable(&iim_clk); - mx53_revision(); + imx_print_silicon_rev("i.MX53", mx53_revision()); clk_disable(&iim_clk); - mx53_display_revision(); /* Set SDHC parents to be PLL2 */ clk_set_parent(&esdhc1_clk, &pll2_sw_clk); diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c index 86f87da..df46967 100644 --- a/arch/arm/mach-mx5/cpu.c +++ b/arch/arm/mach-mx5/cpu.c @@ -18,7 +18,7 @@ #include #include -static int cpu_silicon_rev = -1; +static int mx5_cpu_rev = -1; #define IIM_SREV 0x24 #define MX50_HW_ADADIG_DIGPROG 0xB0 @@ -28,11 +28,14 @@ static int get_mx51_srev(void) void __iomem *iim_base = MX51_IO_ADDRESS(MX51_IIM_BASE_ADDR); u32 rev = readl(iim_base + IIM_SREV) & 0xff; - if (rev == 0x0) + switch (rev) { + case 0x0: return IMX_CHIP_REVISION_2_0; - else if (rev == 0x10) + case 0x2: return IMX_CHIP_REVISION_3_0; - return 0; + default: + return IMX_CHIP_REVISION_UNKNOWN; + } } /* @@ -45,33 +48,13 @@ int mx51_revision(void) if (!cpu_is_mx51()) return -EINVAL; - if (cpu_silicon_rev == -1) - cpu_silicon_rev = get_mx51_srev(); + if (mx5_cpu_rev == -1) + mx5_cpu_rev = get_mx51_srev(); - return cpu_silicon_rev; + return mx5_cpu_rev; } EXPORT_SYMBOL(mx51_revision); -void mx51_display_revision(void) -{ - int rev; - char *srev; - rev = mx51_revision(); - - switch (rev) { - case IMX_CHIP_REVISION_2_0: - srev = IMX_CHIP_REVISION_2_0_STRING; - break; - case IMX_CHIP_REVISION_3_0: - srev = IMX_CHIP_REVISION_3_0_STRING; - break; - default: - srev = IMX_CHIP_REVISION_UNKNOWN_STRING; - } - printk(KERN_INFO "CPU identified as i.MX51, silicon rev %s\n", srev); -} -EXPORT_SYMBOL(mx51_display_revision); - #ifdef CONFIG_NEON /* @@ -121,10 +104,10 @@ int mx53_revision(void) if (!cpu_is_mx53()) return -EINVAL; - if (cpu_silicon_rev == -1) - cpu_silicon_rev = get_mx53_srev(); + if (mx5_cpu_rev == -1) + mx5_cpu_rev = get_mx53_srev(); - return cpu_silicon_rev; + return mx5_cpu_rev; } EXPORT_SYMBOL(mx53_revision); @@ -134,7 +117,7 @@ static int get_mx50_srev(void) u32 rev; if (!anatop) { - cpu_silicon_rev = -EINVAL; + mx5_cpu_rev = -EINVAL; return 0; } @@ -159,36 +142,13 @@ int mx50_revision(void) if (!cpu_is_mx50()) return -EINVAL; - if (cpu_silicon_rev == -1) - cpu_silicon_rev = get_mx50_srev(); + if (mx5_cpu_rev == -1) + mx5_cpu_rev = get_mx50_srev(); - return cpu_silicon_rev; + return mx5_cpu_rev; } EXPORT_SYMBOL(mx50_revision); -void mx53_display_revision(void) -{ - int rev; - char *srev; - rev = mx53_revision(); - - switch (rev) { - case IMX_CHIP_REVISION_1_0: - srev = IMX_CHIP_REVISION_1_0_STRING; - break; - case IMX_CHIP_REVISION_2_0: - srev = IMX_CHIP_REVISION_2_0_STRING; - break; - case IMX_CHIP_REVISION_2_1: - srev = IMX_CHIP_REVISION_2_1_STRING; - break; - default: - srev = IMX_CHIP_REVISION_UNKNOWN_STRING; - } - printk(KERN_INFO "CPU identified as i.MX53, silicon rev %s\n", srev); -} -EXPORT_SYMBOL(mx53_display_revision); - static int __init post_cpu_init(void) { unsigned int reg;