From patchwork Tue Aug 23 04:55:42 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Graf X-Patchwork-Id: 111035 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id E51A0B6F6F for ; Tue, 23 Aug 2011 14:56:02 +1000 (EST) Received: from localhost ([::1]:36986 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Qvj1q-0000ZZ-KN for incoming@patchwork.ozlabs.org; Tue, 23 Aug 2011 00:55:58 -0400 Received: from eggs.gnu.org ([140.186.70.92]:42892) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Qvj1f-0000Sr-EK for qemu-devel@nongnu.org; Tue, 23 Aug 2011 00:55:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Qvj1e-0003oQ-4r for qemu-devel@nongnu.org; Tue, 23 Aug 2011 00:55:47 -0400 Received: from cantor2.suse.de ([195.135.220.15]:44826 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Qvj1d-0003o5-SP for qemu-devel@nongnu.org; Tue, 23 Aug 2011 00:55:46 -0400 Received: from relay2.suse.de (charybdis-ext.suse.de [195.135.221.2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id 783F18C5DF; Tue, 23 Aug 2011 06:55:44 +0200 (CEST) From: Alexander Graf To: qemu-devel@nongnu.org Date: Tue, 23 Aug 2011 06:55:42 +0200 Message-Id: <1314075344-20839-2-git-send-email-agraf@suse.de> X-Mailer: git-send-email 1.6.0.2 In-Reply-To: <1314075344-20839-1-git-send-email-agraf@suse.de> References: <1314075344-20839-1-git-send-email-agraf@suse.de> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4-2.6 X-Received-From: 195.135.220.15 Cc: scottwood@freescale.com Subject: [Qemu-devel] [PATCH 1/3] PPC: E500: Add ESR bit definitions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The BookE spec specifies a number of ESR bits. Add defines for them so we can use them later on. Reported-by: Jason Wessel Signed-off-by: Alexander Graf --- target-ppc/cpu.h | 17 ++++++++++++++++- target-ppc/helper.c | 4 ++-- 2 files changed, 18 insertions(+), 3 deletions(-) diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 024eb6f..b8d42e0 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -516,7 +516,22 @@ struct ppc_slb_t { #endif /* Exception state register bits definition */ -#define ESR_ST 23 /* Exception was caused by a store type access. */ +#define ESR_PIL (1 << (63 - 36)) /* Illegal Instruction */ +#define ESR_PPR (1 << (63 - 37)) /* Privileged Instruction */ +#define ESR_PTR (1 << (63 - 38)) /* Trap */ +#define ESR_FP (1 << (63 - 39)) /* Floating-Point Operation */ +#define ESR_ST (1 << (63 - 40)) /* Store Operation */ +#define ESR_AP (1 << (63 - 44)) /* Auxiliary Processor Operation */ +#define ESR_PUO (1 << (63 - 45)) /* Unimplemented Operation */ +#define ESR_BO (1 << (63 - 46)) /* Byte Ordering */ +#define ESR_PIE (1 << (63 - 47)) /* Imprecise exception */ +#define ESR_DATA (1 << (63 - 53)) /* Data Access (Embedded page table) */ +#define ESR_TLBI (1 << (63 - 54)) /* TLB Ineligible (Embedded page table) */ +#define ESR_PT (1 << (63 - 55)) /* Page Table (Embedded page table) */ +#define ESR_SPV (1 << (63 - 56)) /* SPE/VMX operation */ +#define ESR_EPID (1 << (63 - 57)) /* External Process ID operation */ +#define ESR_VLEMI (1 << (63 - 58)) /* VLE operation */ +#define ESR_MIF (1 << (63 - 62)) /* Misaligned instruction (VLE) */ enum { POWERPC_FLAG_NONE = 0x00000000, diff --git a/target-ppc/helper.c b/target-ppc/helper.c index 3abab1a..c23d4a4 100644 --- a/target-ppc/helper.c +++ b/target-ppc/helper.c @@ -1837,7 +1837,7 @@ int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, env->exception_index = POWERPC_EXCP_DTLB; env->error_code = 0; env->spr[SPR_BOOKE_DEAR] = address; - env->spr[SPR_BOOKE_ESR] = rw ? 1 << ESR_ST : 0; + env->spr[SPR_BOOKE_ESR] = rw ? ESR_ST : 0; return -1; case POWERPC_MMU_REAL: cpu_abort(env, "PowerPC in real mode should never raise " @@ -1861,7 +1861,7 @@ int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, } else if ((env->mmu_model == POWERPC_MMU_BOOKE) || (env->mmu_model == POWERPC_MMU_BOOKE206)) { env->spr[SPR_BOOKE_DEAR] = address; - env->spr[SPR_BOOKE_ESR] = rw ? 1 << ESR_ST : 0; + env->spr[SPR_BOOKE_ESR] = rw ? ESR_ST : 0; } else { env->spr[SPR_DAR] = address; if (rw == 1) {