From patchwork Sun Aug 21 17:05:14 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dong Aisheng X-Patchwork-Id: 110836 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Received: from merlin.infradead.org (merlin.infradead.org [IPv6:2001:4978:20e::2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 1F9EAB6F62 for ; Mon, 22 Aug 2011 02:53:14 +1000 (EST) Received: from canuck.infradead.org ([134.117.69.58]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QvBGc-00084H-Fz; Sun, 21 Aug 2011 16:53:02 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1QvBGb-0004Hk-Uj; Sun, 21 Aug 2011 16:52:57 +0000 Received: from db3ehsobe006.messaging.microsoft.com ([213.199.154.144] helo=DB3EHSOBE006.bigfish.com) by canuck.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QvBGX-0004GM-9p for linux-arm-kernel@lists.infradead.org; Sun, 21 Aug 2011 16:52:54 +0000 Received: from mail67-db3-R.bigfish.com (10.3.81.253) by DB3EHSOBE006.bigfish.com (10.3.84.26) with Microsoft SMTP Server id 14.1.225.22; Sun, 21 Aug 2011 16:52:50 +0000 Received: from mail67-db3 (localhost.localdomain [127.0.0.1]) by mail67-db3-R.bigfish.com (Postfix) with ESMTP id 42D1E11F81D2; Sun, 21 Aug 2011 16:52:50 +0000 (UTC) X-SpamScore: 3 X-BigFish: VS3(zzzz1202h1082kzz8275bhz2dh2a8h668h839h61h) X-Spam-TCS-SCL: 0:0 X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPVD:NLI; H:mail.freescale.net; RD:none; EFVD:NLI Received: from mail67-db3 (localhost.localdomain [127.0.0.1]) by mail67-db3 (MessageSwitch) id 1313945569782116_10101; Sun, 21 Aug 2011 16:52:49 +0000 (UTC) Received: from DB3EHSMHS005.bigfish.com (unknown [10.3.81.241]) by mail67-db3.bigfish.com (Postfix) with ESMTP id AF514640053; Sun, 21 Aug 2011 16:52:49 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by DB3EHSMHS005.bigfish.com (10.3.87.105) with Microsoft SMTP Server (TLS) id 14.1.225.22; Sun, 21 Aug 2011 16:52:49 +0000 Received: from az33smr02.freescale.net (10.64.34.200) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server id 14.1.323.2; Sun, 21 Aug 2011 11:52:47 -0500 Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by az33smr02.freescale.net (8.13.1/8.13.0) with ESMTP id p7LGqiHu021293; Sun, 21 Aug 2011 11:52:45 -0500 (CDT) From: Dong Aisheng To: Subject: [PATCH 3/3] arm: mxs: disable clock-gates when setting saif-clocks Date: Mon, 22 Aug 2011 01:05:14 +0800 Message-ID: <1313946314-3891-1-git-send-email-b29396@freescale.com> X-Mailer: git-send-email 1.7.0.4 MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110821_125253_610680_5379F884 X-CRM114-Status: GOOD ( 15.54 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [213.199.154.144 listed in list.dnswl.org] Cc: alsa-devel@alsa-project.org, broonie@opensource.wolfsonmicro.com, s.hauer@pengutronix.de, lrg@ti.com, w.sang@pengutronix.de X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org From: Dong Aisheng-B29396 New divides should only be written when gates are off. Reported-by: Dong Aisheng Signed-off-by: Wolfram Sang --- BTW, i did a minus change based on wolfram's patch or the saif will not work. Change + __raw_writel(clkgate, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs##_SET); \ to + __raw_writel(reg & ~clkgate, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs##_SET); \ It seemed HW_CLKCTRL_##rs##_SET did not work well. (i did not find HW_CLKCTRL_SAIFx_SET in spec). --- arch/arm/mach-mxs/clock-mx28.c | 7 +++++-- arch/arm/mach-mxs/regs-clkctrl-mx28.h | 2 ++ 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c index 2a2db65..d1d119a 100644 --- a/arch/arm/mach-mxs/clock-mx28.c +++ b/arch/arm/mach-mxs/clock-mx28.c @@ -438,7 +438,7 @@ _CLK_SET_RATE1(xbus_clk, XBUS) static int name##_set_rate(struct clk *clk, unsigned long rate) \ { \ u16 div; \ - u32 reg; \ + u32 reg, clkgate; \ u64 lrate; \ unsigned long parent_rate; \ int i; \ @@ -455,7 +455,8 @@ static int name##_set_rate(struct clk *clk, unsigned long rate) \ return -EINVAL; \ \ reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \ - reg &= ~BM_CLKCTRL_##rs##_DIV; \ + clkgate = reg & BM_CLKCTRL_##rs##_CLKGATE; \ + reg &= ~(BM_CLKCTRL_##rs##_DIV | BM_CLKCTRL_##rs##_CLKGATE); \ reg |= div << BP_CLKCTRL_##rs##_DIV; \ __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \ \ @@ -468,6 +469,8 @@ static int name##_set_rate(struct clk *clk, unsigned long rate) \ return -ETIMEDOUT; \ } \ \ + __raw_writel(reg & ~clkgate, \ + CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \ return 0; \ } diff --git a/arch/arm/mach-mxs/regs-clkctrl-mx28.h b/arch/arm/mach-mxs/regs-clkctrl-mx28.h index 7d1b061..08749b3 100644 --- a/arch/arm/mach-mxs/regs-clkctrl-mx28.h +++ b/arch/arm/mach-mxs/regs-clkctrl-mx28.h @@ -285,6 +285,7 @@ (((v) << 0) & BM_CLKCTRL_EMI_DIV_EMI) #define HW_CLKCTRL_SAIF0 (0x00000100) +#define HW_CLKCTRL_SAIF0_SET (0x00000104) #define BP_CLKCTRL_SAIF0_CLKGATE 31 #define BM_CLKCTRL_SAIF0_CLKGATE 0x80000000 @@ -296,6 +297,7 @@ (((v) << 0) & BM_CLKCTRL_SAIF0_DIV) #define HW_CLKCTRL_SAIF1 (0x00000110) +#define HW_CLKCTRL_SAIF1_SET (0x00000114) #define BP_CLKCTRL_SAIF1_CLKGATE 31 #define BM_CLKCTRL_SAIF1_CLKGATE 0x80000000