diff mbox series

rs6000: Improve p9-dimode* testcases

Message ID 8067112badb3fbf4e80d4e697e6cd29459b1b155.1559043386.git.segher@kernel.crashing.org
State New
Headers show
Series rs6000: Improve p9-dimode* testcases | expand

Commit Message

Segher Boessenkool May 28, 2019, 11:41 a.m. UTC 
This removes the unnecessary restriction to 32-bit (all three ways).
It also scans for mtvsr*, not just mtvsrd.  Finally, it uses the "wa"
constraints instead of "wi" in the inline asm statements.

Tested as usual; committing to trunk.


Segher


2019-05-28  Segher Boessenkool  <segher@kernel.crashing.org>

gcc/testsuite/
	* gcc.target/powerpc/p9-dimode1.c: Don't restrict to -m64.  Check for
	all mtvsr*, not just mtvsrd.  Use "wa" instead of "wi" constraints.
	* gcc.target/powerpc/p9-dimode2.c: Ditto.

---
 gcc/testsuite/gcc.target/powerpc/p9-dimode1.c | 14 +++++---------
 gcc/testsuite/gcc.target/powerpc/p9-dimode2.c | 14 +++++---------
 2 files changed, 10 insertions(+), 18 deletions(-)
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/powerpc/p9-dimode1.c b/gcc/testsuite/gcc.target/powerpc/p9-dimode1.c
index 424ddb5..b2cd3d6 100644
--- a/gcc/testsuite/gcc.target/powerpc/p9-dimode1.c
+++ b/gcc/testsuite/gcc.target/powerpc/p9-dimode1.c
@@ -1,21 +1,17 @@ 
-/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
+/* { dg-do compile { target { powerpc*-*-* } } } */
 /* { dg-require-effective-target powerpc_p9vector_ok } */
 /* { dg-options "-mdejagnu-cpu=power9 -O2" } */
 
 /* Verify P9 changes to allow DImode into Altivec registers, and generate
    constants using XXSPLTIB.  */
 
-#ifndef _ARCH_PPC64
-#error "This code is 64-bit."
-#endif
-
 double
 p9_zero (void)
 {
   long l = 0;
   double ret;
 
-  __asm__ ("xxlor %x0,%x1,%x1" : "=&d" (ret) : "wi" (l));
+  __asm__ ("xxlor %x0,%x1,%x1" : "=&d" (ret) : "wa" (l));
 
   return ret;
 }
@@ -26,7 +22,7 @@  p9_plus_1 (void)
   long l = 1;
   double ret;
 
-  __asm__ ("xxlor %x0,%x1,%x1" : "=&d" (ret) : "wi" (l));
+  __asm__ ("xxlor %x0,%x1,%x1" : "=&d" (ret) : "wa" (l));
 
   return ret;
 }
@@ -37,13 +33,13 @@  p9_minus_1 (void)
   long l = -1;
   double ret;
 
-  __asm__ ("xxlor %x0,%x1,%x1" : "=&d" (ret) : "wi" (l));
+  __asm__ ("xxlor %x0,%x1,%x1" : "=&d" (ret) : "wa" (l));
 
   return ret;
 }
 
 /* { dg-final { scan-assembler     {\mxxspltib\M} } } */
-/* { dg-final { scan-assembler-not {\mmtvsrd\M}   } } */
+/* { dg-final { scan-assembler-not {\mmtvsr}      } } */
 /* { dg-final { scan-assembler-not {\mlfd\M}      } } */
 /* { dg-final { scan-assembler-not {\mld\M}       } } */
 /* { dg-final { scan-assembler-not {\mlxsd\M}     } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/p9-dimode2.c b/gcc/testsuite/gcc.target/powerpc/p9-dimode2.c
index dc3c360..c2196a2 100644
--- a/gcc/testsuite/gcc.target/powerpc/p9-dimode2.c
+++ b/gcc/testsuite/gcc.target/powerpc/p9-dimode2.c
@@ -1,13 +1,9 @@ 
-/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
+/* { dg-do compile { target { powerpc*-*-* } } } */
 /* { dg-require-effective-target powerpc_p9vector_ok } */
 /* { dg-options "-mdejagnu-cpu=power9 -O2" } */
 
-/* Verify that large integer constants are loaded via direct move instead of being
-   loaded from memory.  */
-
-#ifndef _ARCH_PPC64
-#error "This code is 64-bit."
-#endif
+/* Verify that large integer constants are loaded via direct move instead of
+   being loaded from memory.  */
 
 double
 p9_large (void)
@@ -15,12 +11,12 @@  p9_large (void)
   long l = 0x12345678;
   double ret;
 
-  __asm__ ("xxlor %x0,%x1,%x1" : "=&d" (ret) : "wi" (l));
+  __asm__ ("xxlor %x0,%x1,%x1" : "=&d" (ret) : "wa" (l));
 
   return ret;
 }
 
-/* { dg-final { scan-assembler     {\mmtvsrd\M} } } */
+/* { dg-final { scan-assembler     {\mmtvsr}    } } */
 /* { dg-final { scan-assembler-not {\mld\M}     } } */
 /* { dg-final { scan-assembler-not {\mlfd\M}    } } */
 /* { dg-final { scan-assembler-not {\mlxsd\M}   } } */