[U-Boot,3/6] riscv: ae350: add imply v5l2 cache controller

Message ID	20190528093914.4672-4-uboot@andestech.com
State	Superseded
Delegated to:	Andes
Headers	show Return-Path: <u-boot-bounces@lists.denx.de> From: Andes <uboot@andestech.com> To: <u-boot@lists.denx.de> Date: Tue, 28 May 2019 17:39:11 +0800 Message-ID: <20190528093914.4672-4-uboot@andestech.com> In-Reply-To: <20190528093914.4672-1-uboot@andestech.com> References: <20190528093914.4672-1-uboot@andestech.com> MIME-Version: 1.0 Cc: trini@konsulko.com, greentime@andestech.com, rickchen36@gmail.com Subject: [U-Boot] [PATCH 3/6] riscv: ae350: add imply v5l2 cache controller Precedence: list Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" <u-boot-bounces@lists.denx.de>
Series	Support Andes RISC-V l2cache on AE350 platform \| expand [U-Boot,0/6] Support Andes RISC-V l2cache on AE350 platform [U-Boot,1/6] dm: cache: add v5l2 cache controller driver [U-Boot,2/6] riscv: ae350: use the v5l2 driver to configure the cache [U-Boot,3/6] riscv: ae350: add imply v5l2 cache controller [U-Boot,4/6] riscv: cache: Flush L2 cache before jump to linux [U-Boot,5/6] riscv: dts: move out AE350 L2 node from cpus node [U-Boot,6/6] riscv: ax25: use CCTL to flush d-cache

Message ID

20190528093914.4672-4-uboot@andestech.com

State

Superseded

Delegated to:

Andes

Headers

From: Andes <uboot@andestech.com>
To: <u-boot@lists.denx.de>
Date: Tue, 28 May 2019 17:39:11 +0800
Message-ID: <20190528093914.4672-4-uboot@andestech.com>
In-Reply-To: <20190528093914.4672-1-uboot@andestech.com>
References: <20190528093914.4672-1-uboot@andestech.com>
MIME-Version: 1.0
Cc: trini@konsulko.com, greentime@andestech.com, rickchen36@gmail.com
Subject: [U-Boot] [PATCH 3/6] riscv: ae350: add imply v5l2 cache controller
Precedence: list
Content-Type: text/plain; charset="utf-8"
Content-Transfer-Encoding: base64
Errors-To: u-boot-bounces@lists.denx.de
Sender: "U-Boot" <u-boot-bounces@lists.denx.de>

Series

Support Andes RISC-V l2cache on AE350 platform | expand

From: Rick Chen <rick@andestech.com> Select the v5l2 UCLASS_CACHE driver for AE350. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> --- board/AndesTech/ax25-ae350/Kconfig | 1 + 1 file changed, 1 insertion(+)

Comments

Bin Meng June 4, 2019, 2:48 a.m. UTC | #1

Hi Rick,

On Tue, May 28, 2019 at 5:44 PM Andes <uboot@andestech.com> wrote:
>
> From: Rick Chen <rick@andestech.com>
>
> Select the v5l2 UCLASS_CACHE driver for AE350.
>
> Signed-off-by: Rick Chen <rick@andestech.com>
> Cc: Greentime Hu <greentime@andestech.com>
> ---
>  board/AndesTech/ax25-ae350/Kconfig | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/board/AndesTech/ax25-ae350/Kconfig b/board/AndesTech/ax25-ae350/Kconfig
> index 5e682b6..dd299d9 100644
> --- a/board/AndesTech/ax25-ae350/Kconfig
> +++ b/board/AndesTech/ax25-ae350/Kconfig
> @@ -25,5 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
>         def_bool y
>         select RISCV_NDS
>         imply SMP
> +       imply V5L2_CACHE

I believe L2 cache is a CPU specific feature, hence this should be
implied from arch/riscv/cpu/ax25/Kconfig

Regards,
Bin

Rick Chen June 5, 2019, 9:25 a.m. UTC | #2

Hi Bin

>
> Hi Rick,
>
> On Tue, May 28, 2019 at 5:44 PM Andes <uboot@andestech.com> wrote:
> >
> > From: Rick Chen <rick@andestech.com>
> >
> > Select the v5l2 UCLASS_CACHE driver for AE350.
> >
> > Signed-off-by: Rick Chen <rick@andestech.com>
> > Cc: Greentime Hu <greentime@andestech.com>
> > ---
> >  board/AndesTech/ax25-ae350/Kconfig | 1 +
> >  1 file changed, 1 insertion(+)
> >
> > diff --git a/board/AndesTech/ax25-ae350/Kconfig b/board/AndesTech/ax25-ae350/Kconfig
> > index 5e682b6..dd299d9 100644
> > --- a/board/AndesTech/ax25-ae350/Kconfig
> > +++ b/board/AndesTech/ax25-ae350/Kconfig
> > @@ -25,5 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
> >         def_bool y
> >         select RISCV_NDS
> >         imply SMP
> > +       imply V5L2_CACHE
>
> I believe L2 cache is a CPU specific feature, hence this should be
> implied from arch/riscv/cpu/ax25/Kconfig

OK
I will move it to arch/riscv/cpu/ax25/Kconfig

Thanks
Rick

>
> Regards,
> Bin

diff --git a/board/AndesTech/ax25-ae350/Kconfig b/board/AndesTech/ax25-ae350/Kconfig
index 5e682b6..dd299d9 100644
--- a/board/AndesTech/ax25-ae350/Kconfig
+++ b/board/AndesTech/ax25-ae350/Kconfig
@@ -25,5 +25,6 @@  config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select RISCV_NDS
 	imply SMP
+	imply V5L2_CACHE
 
 endif

[U-Boot,3/6] riscv: ae350: add imply v5l2 cache controller

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