From patchwork Wed Aug 17 20:46:33 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryce Lanham X-Patchwork-Id: 110486 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 8A076B6FA0 for ; Thu, 18 Aug 2011 10:53:39 +1000 (EST) Received: from localhost ([::1]:48119 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QtqrU-00010d-7i for incoming@patchwork.ozlabs.org; Wed, 17 Aug 2011 20:53:32 -0400 Received: from eggs.gnu.org ([140.186.70.92]:47140) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Qtn2r-0006TB-Li for qemu-devel@nongnu.org; Wed, 17 Aug 2011 16:49:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Qtn2q-0006lI-Jy for qemu-devel@nongnu.org; Wed, 17 Aug 2011 16:49:01 -0400 Received: from mail-gx0-f173.google.com ([209.85.161.173]:54221) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Qtn2q-0006aR-H4 for qemu-devel@nongnu.org; Wed, 17 Aug 2011 16:49:00 -0400 Received: by mail-gx0-f173.google.com with SMTP id 26so1230323gxk.4 for ; Wed, 17 Aug 2011 13:49:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=RoOx0Fa9j+mI+Fxvcxqz8V/rGDMLGneJNA1OzoEJlqg=; b=sm3Wnss7KjpLyuiV0eQ7ws1jqoY7wxvyY5DeZEaOGg564tcnpPsXdxeLUDYBXYh1S2 y9JfDrgXXCKxpPWaMgaBPuQy547MwPEKNAHp9DvSz+KIhyFSMqMcW2Nb9M7hXPIAVniN osPiVryuVtOTOju5mtiLfzLbxW7Tvx+ZB0T74= Received: by 10.236.187.106 with SMTP id x70mr4922033yhm.142.1313614140282; Wed, 17 Aug 2011 13:49:00 -0700 (PDT) Received: from localhost.localdomain (betelgeuse.cs.uchicago.edu [128.135.24.226]) by mx.google.com with ESMTPS id a29sm1237029yhj.59.2011.08.17.13.48.58 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 17 Aug 2011 13:48:59 -0700 (PDT) From: Bryce Lanham To: qemu-devel@nongnu.org Date: Wed, 17 Aug 2011 15:46:33 -0500 Message-Id: <1313614076-28878-29-git-send-email-blanham@gmail.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1313614076-28878-1-git-send-email-blanham@gmail.com> References: <1313614076-28878-1-git-send-email-blanham@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 209.85.161.173 Cc: Laurent Vivier Subject: [Qemu-devel] [PATCH 028/111] m68k: allow fpu to manage double data type. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Laurent Vivier This patch allows to manage instructions like "fcmpd #2.2, %fp0". Original function manages only data accessed through an address register. Signed-off-by: Laurent Vivier --- target-m68k/translate.c | 48 ++++++++++++++-------------------------------- 1 files changed, 15 insertions(+), 33 deletions(-) diff --git a/target-m68k/translate.c b/target-m68k/translate.c index d4d2f44..a91f557 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -2939,6 +2939,7 @@ DISAS_INSN(fpu) TCGv_i64 dest; TCGv_i64 res; TCGv tmp32; + TCGv reg; int round; int set_dest; int opsize; @@ -3111,40 +3112,21 @@ DISAS_INSN(fpu) goto undef; } if (opsize == OS_DOUBLE) { - tmp32 = tcg_temp_new_i32(); - tcg_gen_mov_i32(tmp32, AREG(insn, 0)); - switch ((insn >> 3) & 7) { - case 2: - case 3: - break; - case 4: - tcg_gen_addi_i32(tmp32, tmp32, -8); - break; - case 5: - offset = ldsw_code(s->pc); - s->pc += 2; - tcg_gen_addi_i32(tmp32, tmp32, offset); - break; - case 7: - offset = ldsw_code(s->pc); - offset += s->pc - 2; - s->pc += 2; - tcg_gen_addi_i32(tmp32, tmp32, offset); - break; - default: - goto undef; - } - src = gen_load64(s, tmp32); - switch ((insn >> 3) & 7) { - case 3: - tcg_gen_addi_i32(tmp32, tmp32, 8); - tcg_gen_mov_i32(AREG(insn, 0), tmp32); - break; - case 4: - tcg_gen_mov_i32(AREG(insn, 0), tmp32); - break; + if ((insn & 0x3f) == 0x3c) { + src = gen_load64(s, tcg_const_i32(s->pc)); + s->pc += 8; + } else { + tmp32 = gen_lea(s, insn, opsize); + if (IS_NULL_QREG(tmp32)) { + gen_addr_fault(s); + return; + } + src = gen_load64(s, tmp32); + if ( ((insn >> 3) & 7) == 3) { /* post-increment */ + reg = AREG(insn, 0); + tcg_gen_addi_i32(reg, reg, opsize_bytes(opsize)); + } } - tcg_temp_free_i32(tmp32); } else { SRC_EA(tmp32, opsize, 1, NULL); src = tcg_temp_new_i64();