From patchwork Wed Aug 17 20:46:24 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryce Lanham X-Patchwork-Id: 110465 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id AC992B6F86 for ; Thu, 18 Aug 2011 09:39:43 +1000 (EST) Received: from localhost ([::1]:51107 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Qtn3r-0008Qr-KA for incoming@patchwork.ozlabs.org; Wed, 17 Aug 2011 16:50:03 -0400 Received: from eggs.gnu.org ([140.186.70.92]:46984) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Qtn2e-0005vi-8h for qemu-devel@nongnu.org; Wed, 17 Aug 2011 16:48:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Qtn2c-0006hg-Qw for qemu-devel@nongnu.org; Wed, 17 Aug 2011 16:48:48 -0400 Received: from mail-gw0-f45.google.com ([74.125.83.45]:62061) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Qtn2c-0006dP-Ir for qemu-devel@nongnu.org; Wed, 17 Aug 2011 16:48:46 -0400 Received: by mail-gw0-f45.google.com with SMTP id 19so553866gwb.4 for ; Wed, 17 Aug 2011 13:48:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=TirluDerLKJ6oOmZ3w1nAIluVRet2qgLmgF/A5F/3/c=; b=db6TL7WyW7EabCirwxnelsBV2Zgdh2+WYBJWHZwlDkZ2CQoBgfcRjpGuybMqtZJB5K LXYnZxjIbU4umbqXGbWVwYIRpIjP/1yS+rj0o/VHCxG6Ru35+BrBQgxigy0WAeEOsF0s KqnxK0I7fwiLHJM5HuXFBnyXfSyIu8D/y8NSg= Received: by 10.90.10.29 with SMTP id 29mr1612714agj.63.1313614126259; Wed, 17 Aug 2011 13:48:46 -0700 (PDT) Received: from localhost.localdomain (betelgeuse.cs.uchicago.edu [128.135.24.226]) by mx.google.com with ESMTPS id a29sm1237029yhj.59.2011.08.17.13.48.44 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 17 Aug 2011 13:48:45 -0700 (PDT) From: Bryce Lanham To: qemu-devel@nongnu.org Date: Wed, 17 Aug 2011 15:46:24 -0500 Message-Id: <1313614076-28878-20-git-send-email-blanham@gmail.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1313614076-28878-1-git-send-email-blanham@gmail.com> References: <1313614076-28878-1-git-send-email-blanham@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 74.125.83.45 Cc: Andreas Schwab , Laurent Vivier Subject: [Qemu-devel] [PATCH 019/111] m68k: add fpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Laurent Vivier Modify "fpu" instruction to be compatible with 680x0 family and attach it to FPU feature (in addition to CF_FPU). Signed-off-by: Andreas Schwab Signed-off-by: Laurent Vivier --- target-m68k/translate.c | 49 ++++++++++++++++++++++++++++++++++++++++------ 1 files changed, 42 insertions(+), 7 deletions(-) diff --git a/target-m68k/translate.c b/target-m68k/translate.c index 0321349..8fb71b8 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -2342,18 +2342,43 @@ DISAS_INSN(fpu) case 7: { TCGv addr; + int incr; uint16_t mask; int i; - if ((ext & 0x1f00) != 0x1000 || (ext & 0xff) == 0) + if ((ext & 0xf00) != 0 || (ext & 0xff) == 0) goto undef; - tmp32 = gen_lea(s, insn, OS_LONG); - if (IS_NULL_QREG(tmp32)) { - gen_addr_fault(s); - return; + if ((ext & 0x1000) == 0 && !m68k_feature(s->env, M68K_FEATURE_FPU)) + goto undef; + if ((insn & 070) == 040) + tmp32 = AREG(insn, 0); + else { + tmp32 = gen_lea(s, insn, OS_LONG); + if (IS_NULL_QREG(tmp32)) { + gen_addr_fault(s); + return; + } } addr = tcg_temp_new_i32(); tcg_gen_mov_i32(addr, tmp32); mask = 0x80; + if (m68k_feature(s->env, M68K_FEATURE_FPU)) + incr = 12; + else + incr = 8; + if ((ext & (1 << 13)) && (insn & 070) == 040) { + for (i = 0; i < 8; i++) { + if (ext & mask) { + s->is_mem = 1; + dest = FREG(i, 7); + tcg_gen_subi_i32(addr, addr, incr); + tcg_gen_mov_i32(AREG(insn, 0), addr); + tcg_gen_qemu_stf64(dest, addr, IS_USER(s)); + } + mask >>= 1; + } + tcg_temp_free_i32(addr); + return; + } for (i = 0; i < 8; i++) { if (ext & mask) { s->is_mem = 1; @@ -2365,8 +2390,11 @@ DISAS_INSN(fpu) /* load */ tcg_gen_qemu_ldf64(dest, addr, IS_USER(s)); } - if (ext & (mask - 1)) - tcg_gen_addi_i32(addr, addr, 8); + if (ext & (mask - 1) || (insn & 070) == 030) { + tcg_gen_addi_i32(addr, addr, incr); + if ((insn & 070) == 030) + tcg_gen_mov_i32(AREG(insn, 0), addr); + } } mask >>= 1; } @@ -2474,6 +2502,12 @@ DISAS_INSN(fpu) case 0x23: case 0x63: case 0x67: /* fmul */ gen_helper_mul_f64(res, cpu_env, res, src); break; + case 0x24: /* fsgldiv */ + gen_helper_div_f64(res, cpu_env, res, src); + break; + case 0x27: /* fsglmul */ + gen_helper_mul_f64(res, cpu_env, res, src); + break; case 0x28: case 0x68: case 0x6c: /* fsub */ gen_helper_sub_f64(res, cpu_env, res, src); break; @@ -3156,6 +3190,7 @@ void register_m68k_insns (CPUM68KState *env) INSN(fbcc, f280, ffc0, CF_FPU); INSN(frestore, f340, ffc0, CF_FPU); INSN(fsave, f340, ffc0, CF_FPU); + INSN(fpu, f200, ffc0, FPU); INSN(fbcc, f280, ffc0, FPU); INSN(frestore, f340, ffc0, FPU); INSN(fsave, f340, ffc0, FPU);