@@ -89,6 +89,27 @@ Required properties:
"fsl,imx8qm-clock"
"fsl,imx8qxp-clock"
followed by "fsl,scu-clk"
+- #address-cells: Should be 1.
+- #size-cells: Should be 0.
+
+Sub nodes are required to represent all available SCU clocks within this
+hardware subsystem and the following properties are needed:
+
+- reg: Should contain the Resource ID of this SCU clock.
+- #clock-cells: Should be 1.
+- clock-indices: Index of all clock types supported by this SCU clock.
+ The order should match the clock-output-names array.
+ Refer to <include/dt-bindings/firmware/imx/rsrc.h> for
+ available clock types supported by SCU.
+- clock-output-names: Shall be the corresponding names of the outputs.
+- power-domains: Should contain the power domain used by this SCU clock.
+
+Optional properties:
+- clocks: Shall be the input parent clock(s) phandle for the clock.
+ For multiplexed clocks, the list order must match the hardware
+ programming order.
+
+Legacy Clock binding (No sub-nodes which is DEPRECATED):
- #clock-cells: Should be 1. Contains the Clock ID value.
- clocks: List of clock specifiers, must contain an entry for
each required entry in clock-names
@@ -144,6 +165,21 @@ lsio_mu1: mailbox@5d1c0000 {
#mbox-cells = <2>;
};
+conn-scu-clock-controller {
+ compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ uart0_clk: clock-scu@57 {
+ reg = <57>;
+ #clock-cells = <1>;
+ clock-indices = <IMX_SC_PM_CLK_PER>;
+ clock-output-names = "uart0_clk";
+ power-domains = <&pd IMX_SC_R_UART_0>;
+ };
+ ...
+}
+
firmware {
scu {
compatible = "fsl,imx-scu";
@@ -160,11 +196,6 @@ firmware {
&lsio_mu1 1 3
&lsio_mu1 3 3>;
- clk: clk {
- compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
- #clock-cells = <1>;
- };
-
iomuxc {
compatible = "fsl,imx8qxp-iomuxc";
@@ -192,8 +223,6 @@ serial@5a060000 {
...
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart0>;
- clocks = <&clk IMX8QXP_UART0_CLK>,
- <&clk IMX8QXP_UART0_IPG_CLK>;
- clock-names = "per", "ipg";
+ clocks = <&uart0_clk IMX_SC_PM_CLK_PER>;
power-domains = <&pd IMX_SC_R_UART_0>;
};
@@ -547,4 +547,21 @@
#define IMX_SC_R_ATTESTATION 545
#define IMX_SC_R_LAST 546
+/*
+ * Defines for SC PM CLK
+ */
+#define IMX_SC_PM_CLK_SLV_BUS 0 /* Slave bus clock */
+#define IMX_SC_PM_CLK_MST_BUS 1 /* Master bus clock */
+#define IMX_SC_PM_CLK_PER 2 /* Peripheral clock */
+#define IMX_SC_PM_CLK_PHY 3 /* Phy clock */
+#define IMX_SC_PM_CLK_MISC 4 /* Misc clock */
+#define IMX_SC_PM_CLK_MISC0 0 /* Misc 0 clock */
+#define IMX_SC_PM_CLK_MISC1 1 /* Misc 1 clock */
+#define IMX_SC_PM_CLK_MISC2 2 /* Misc 2 clock */
+#define IMX_SC_PM_CLK_MISC3 3 /* Misc 3 clock */
+#define IMX_SC_PM_CLK_MISC4 4 /* Misc 4 clock */
+#define IMX_SC_PM_CLK_CPU 2 /* CPU clock */
+#define IMX_SC_PM_CLK_PLL 4 /* PLL */
+#define IMX_SC_PM_CLK_BYPASS 4 /* Bypass clock */
+
#endif /* __DT_BINDINGS_RSCRC_IMX_H */