Patchwork [7/8] added move16, cinva, pflush instructions, and disabled abort on execution of frestore/fsave

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Submitter Bryce Lanham
Date Aug. 17, 2011, 10:09 p.m.
Message ID <1313618952-14774-9-git-send-email-blanham@gmail.com>
Download mbox | patch
Permalink /patch/110458/
State New
Headers show

Comments

Bryce Lanham - Aug. 17, 2011, 10:09 p.m.
Signed-off-by: Bryce Lanham <blanham@gmail.com>
---
 target-m68k/translate.c |  108 ++++++++++++++++++++++++++++++++++++++++++-----
 1 files changed, 97 insertions(+), 11 deletions(-)

Patch

diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index 0be011e..1975a06 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -29,6 +29,8 @@ 
 #include "tcg-op.h"
 #include "qemu-log.h"
 
+#include "sysemu.h"
+
 #include "helpers.h"
 #define GEN_HELPER 1
 #include "helpers.h"
@@ -179,7 +181,6 @@  static inline void gen_flush_cc_op(DisasContext *s)
         tcg_gen_movi_i32(QREG_CC_OP, s->cc_op);
 }
 
-
 /* Generate a jump to an immediate address.  */
 static void gen_jmp_im(DisasContext *s, uint32_t dest)
 {
@@ -191,7 +192,7 @@  static void gen_jmp_im(DisasContext *s, uint32_t dest)
 static void gen_exception(DisasContext *s, uint32_t where, int nr)
 {
     gen_flush_cc_op(s);
-    gen_jmp_im(s, where);
+    gen_jmp_im(s,where);
     gen_helper_raise_exception(tcg_const_i32(nr));
 }
 
@@ -1768,7 +1769,7 @@  DISAS_INSN(arith_im)
         tcg_gen_addi_i32(dest, dest, im);
         gen_update_cc_add(dest, tcg_const_i32(im));
         SET_X_FLAG(opsize, dest, tcg_const_i32(im));
-	SET_CC_OP(opsize, ADD);
+    SET_CC_OP(opsize, ADD);
         break;
     case 5: /* eori */
         tcg_gen_xori_i32(dest, src1, im);
@@ -3445,7 +3446,7 @@  DISAS_INSN(move_from_sr)
 {
     TCGv sr;
 
-    if (IS_USER(s)) {    /* FIXME: not privileged on 68000 */
+    if (IS_USER(s)) { /* FICME: not privledged on 68000 */
         gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
         return;
     }
@@ -3829,8 +3830,8 @@  DISAS_INSN(fpu)
     case 0x33: case 0x34: case 0x35:
     case 0x36: case 0x37:
         gen_helper_sincos_FP0_FP1(cpu_env);
-        gen_op_store_fpr_FP0(REG(ext, 7));	/* sin */
-        gen_op_store_fpr_FP1(REG(ext, 0));	/* cos */
+        gen_op_store_fpr_FP0(REG(ext, 7));  /* sin */
+        gen_op_store_fpr_FP1(REG(ext, 0));  /* cos */
         break;
     case 0x38: /* fcmp */
         gen_op_load_fpr_FP1(REG(ext, 7));
@@ -3996,17 +3997,27 @@  DISAS_INSN(fscc_reg)
     tcg_gen_andi_i32(reg, reg, 0xffffff00);
     gen_set_label(l1);
 }
-
+/* abort is disabled here, as pasing through these instructions merely breaks the fpu
+ *  preferable when we want to get the machine booting first
+ */
 DISAS_INSN(frestore)
 {
     /* TODO: Implement frestore.  */
-    qemu_assert(0, "FRESTORE not implemented");
+ //   qemu_assert(0, "FRESTORE not implemented");
+  // cpu_abort(cpu_single_env, "Illegal instruction: %04x @ %08x",
+    //          insn, s->pc - 2);
+
+
 }
 
 DISAS_INSN(fsave)
 {
     /* TODO: Implement fsave.  */
-    qemu_assert(0, "FSAVE not implemented");
+  //  qemu_assert(0, "FSAVE not implemented");
+  // cpu_abort(cpu_single_env, "Illegal instruction: %04x @ %08x",
+           //   insn, s->pc - 2);
+
+
 }
 
 static inline TCGv gen_mac_extract_word(DisasContext *s, TCGv val, int upper)
@@ -4363,6 +4374,73 @@  register_opcode (disas_proc proc, uint16_t opcode, uint16_t mask)
   }
 }
 
+/* my instructions start here */
+DISAS_INSN(cinva)
+{
+/* Cache invalidate (NOP)*/
+}
+/* page flush acts as a NOP at the moment, as I have not gotten far enough
+ * to test its functionality 
+ * */
+DISAS_INSN(pflush)
+{
+    int opmode = (insn>>3) & 0x3;
+    switch(opmode)
+    {
+        case 0x0:
+        case 0x1:
+        fprintf(stderr,"entry\n");
+        break;
+        case 0x2:
+        case 0x3:
+        fprintf(stderr,"all\n");
+        break;
+
+    }
+    
+
+}
+DISAS_INSN(move16)
+{
+    TCGv src;
+    TCGv s_addr;
+    TCGv d_addr;
+    uint16_t im;
+    if(insn & 0x8){
+        
+                vm_stop(VMSTOP_DEBUG);
+        //abort();
+    }else if(insn & 0x10){
+
+                vm_stop(VMSTOP_DEBUG);
+        //abort();
+
+    }else{
+      
+        d_addr = tcg_temp_new();
+        s_addr = tcg_temp_new();    
+        
+        s_addr = AREG(insn,0);
+        src = gen_load(s, OS_LONG, s_addr, 0); 
+        
+        im = read_im16(s);
+        d_addr = AREG(im,12);
+
+        gen_store(s, OS_LONG, d_addr, src);
+        
+        int i = 0;
+        for(;i <3; i++)
+        {
+            tcg_gen_addi_i32(d_addr,d_addr,4);
+            tcg_gen_addi_i32(s_addr,s_addr,4);
+
+            src = gen_load(s, OS_LONG, s_addr, 0); 
+            gen_store(s, OS_LONG, d_addr, src);
+        }
+    }
+}
+
+
 /* Register m68k opcode handlers.  Order is important.
    Later insn override earlier ones.  */
 void register_m68k_insns (CPUM68KState *env)
@@ -4565,6 +4643,7 @@  void register_m68k_insns (CPUM68KState *env)
     INSN(addx_mem,  d108, f138, M68000);
     INSN(adda,      d1c0, f1c0, CF_ISA_A);
     INSN(adda,      d0c0, f0c0, M68000);
+    /* Bit ops */
     INSN(shift_im,  e080, f0f0, CF_ISA_A);
     INSN(shift_reg, e0a0, f0f0, CF_ISA_A);
     INSN(shift8_im, e000, f0f0, M68000);
@@ -4583,6 +4662,7 @@  void register_m68k_insns (CPUM68KState *env)
     INSN(rotate_mem, e4c0, fcc0, M68000);
     INSN(bitfield_mem,e8c0, f8c0, BITFIELD);
     INSN(bitfield_reg,e8c0, f8f8, BITFIELD);
+    /* FPU */
     INSN(undef_fpu, f000, f000, CF_ISA_A);
     INSN(undef_fpu, f000, f000, M68000);
     INSN(fpu,       f200, ffc0, CF_FPU);
@@ -4593,10 +4673,16 @@  void register_m68k_insns (CPUM68KState *env)
     INSN(fscc_mem,  f240, ffc0, FPU);
     INSN(fscc_reg,  f240, fff8, FPU);
     INSN(fbcc,      f280, ffc0, FPU);
-    INSN(frestore,  f340, ffc0, FPU);
+    INSN(frestore,  f300, ffc0, FPU);
     INSN(fsave,     f340, ffc0, FPU);
     INSN(intouch,   f340, ffc0, CF_ISA_A);
+    /* MMU */
     INSN(cpushl,    f428, ff38, CF_ISA_A);
+    INSN(cpushl,    f478, ff78, M68000);
+    INSN(cinva,     f4d8, f4d8, M68000);
+    INSN(pflush,    f500, f500, M68000);
+    
+    INSN(move16,    f600, f600, M68000);
     INSN(wddata,    fb00, ff00, CF_ISA_A);
     INSN(wdebug,    fbc0, ffc0, CF_ISA_A);
 #ifdef CONFIG_EMULOP
@@ -4684,7 +4770,7 @@  gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
         if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
             gen_io_start();
         dc->insn_pc = dc->pc;
-	disas_m68k_insn(env, dc);
+    disas_m68k_insn(env, dc);
         num_insns++;
     } while (!dc->is_jmp && gen_opc_ptr < gen_opc_end &&
              !env->singlestep_enabled &&