From patchwork Wed Aug 17 20:46:44 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryce Lanham X-Patchwork-Id: 110377 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 2D025B6F98 for ; Thu, 18 Aug 2011 07:55:24 +1000 (EST) Received: from localhost ([::1]:50752 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Qtn3e-0008GJ-4q for incoming@patchwork.ozlabs.org; Wed, 17 Aug 2011 16:49:50 -0400 Received: from eggs.gnu.org ([140.186.70.92]:47234) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Qtn3J-0007jV-QQ for qemu-devel@nongnu.org; Wed, 17 Aug 2011 16:49:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Qtn3D-0006nM-Sx for qemu-devel@nongnu.org; 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Wed, 17 Aug 2011 13:49:22 -0700 (PDT) From: Bryce Lanham To: qemu-devel@nongnu.org Date: Wed, 17 Aug 2011 15:46:44 -0500 Message-Id: <1313614076-28878-40-git-send-email-blanham@gmail.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1313614076-28878-1-git-send-email-blanham@gmail.com> References: <1313614076-28878-1-git-send-email-blanham@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 209.85.160.173 Cc: Laurent Vivier Subject: [Qemu-devel] [PATCH 039/111] m68k: add abcd instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Laurent Vivier Signed-off-by: Laurent Vivier --- target-m68k/helper.c | 38 ++++++++++++++++++++++++++++++++++++++ target-m68k/helpers.h | 2 ++ target-m68k/translate.c | 32 ++++++++++++++++++++++++++++++++ 3 files changed, 72 insertions(+), 0 deletions(-) diff --git a/target-m68k/helper.c b/target-m68k/helper.c index dfa7c10..7d99326 100644 --- a/target-m68k/helper.c +++ b/target-m68k/helper.c @@ -1286,3 +1286,41 @@ void HELPER(bitfield_store)(uint32_t addr, uint32_t offset, uint32_t width, cpu_physical_memory_rw(addr, data, size, 1); #endif } + +uint32_t HELPER(abcd_cc)(CPUState *env, uint32_t src, uint32_t dest) +{ + uint16_t hi, lo; + uint16_t res; + uint32_t flags; + + flags = env->cc_dest; + flags &= ~(CCF_C|CCF_X); + + lo = (src & 0x0f) + (dest & 0x0f); + if (env->cc_x) + lo ++; + hi = (src & 0xf0) + (dest & 0xf0); + + res = hi + lo; + if (lo > 9) + res += 0x06; + + /* C and X flags: set if decimal carry, cleared otherwise */ + + if ((res & 0x3F0) > 0x90) { + res += 0x60; + flags |= CCF_C|CCF_X; + } + + /* Z flag: cleared if nonzero */ + + if (res & 0xff) + flags &= ~CCF_Z; + + dest = (dest & 0xffffff00) | (res & 0xff); + + env->cc_x = (flags & CCF_X) != 0; + env->cc_dest = flags; + + return dest; +} diff --git a/target-m68k/helpers.h b/target-m68k/helpers.h index 4bfb149..f299752 100644 --- a/target-m68k/helpers.h +++ b/target-m68k/helpers.h @@ -81,4 +81,6 @@ DEF_HELPER_1(raise_exception, void, i32) DEF_HELPER_3(bitfield_load, i64, i32, i32, i32); DEF_HELPER_4(bitfield_store, void, i32, i32, i32, i64); + +DEF_HELPER_3(abcd_cc, i32, env, i32, i32); #include "def-helper.h" diff --git a/target-m68k/translate.c b/target-m68k/translate.c index ab2073a..231d87a 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -1065,6 +1065,36 @@ DISAS_INSN(divl) s->cc_op = CC_OP_FLAGS; } +DISAS_INSN(abcd_reg) +{ + TCGv src; + TCGv dest; + + src = DREG(insn, 0); + dest = DREG(insn, 9); + gen_helper_abcd_cc(dest, cpu_env, src, dest); +} + +DISAS_INSN(abcd_mem) +{ + TCGv src; + TCGv addr_src; + TCGv dest; + TCGv addr_dest; + + addr_src = AREG(insn, 0); + tcg_gen_subi_i32(addr_src, addr_src, OS_BYTE); + src = gen_load(s, OS_BYTE, addr_src, 0); + + addr_dest = AREG(insn, 9); + tcg_gen_subi_i32(addr_dest, addr_dest, OS_BYTE); + dest = gen_load(s, OS_BYTE, addr_dest, 0); + + gen_helper_abcd_cc(dest, cpu_env, src, dest); + + gen_store(s, OS_BYTE, addr_dest, dest); +} + DISAS_INSN(addsub) { TCGv reg; @@ -3915,6 +3945,8 @@ void register_m68k_insns (CPUM68KState *env) INSN(and, c000, f000, M68000); INSN(mulw, c0c0, f0c0, CF_ISA_A); INSN(mulw, c0c0, f0c0, M68000); + INSN(abcd_reg, c100, f1f8, M68000); + INSN(abcd_mem, c108, f1f8, M68000); INSN(addsub, d000, f000, CF_ISA_A); INSN(addsub, d000, f000, M68000); INSN(undef, d0c0, f0c0, CF_ISA_A);