From patchwork Wed Aug 17 20:46:47 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryce Lanham X-Patchwork-Id: 110375 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 86457B6F98 for ; Thu, 18 Aug 2011 07:51:59 +1000 (EST) Received: from localhost ([::1]:44851 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Qto1j-0005CF-CD for incoming@patchwork.ozlabs.org; Wed, 17 Aug 2011 17:51:55 -0400 Received: from eggs.gnu.org ([140.186.70.92]:47231) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Qtn3J-0007gd-1V for qemu-devel@nongnu.org; Wed, 17 Aug 2011 16:49:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Qtn3H-0006o6-SM for qemu-devel@nongnu.org; Wed, 17 Aug 2011 16:49:28 -0400 Received: from mail-yx0-f173.google.com ([209.85.213.173]:36963) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Qtn3H-0006fW-Pb for qemu-devel@nongnu.org; Wed, 17 Aug 2011 16:49:27 -0400 Received: by mail-yx0-f173.google.com with SMTP id 3so1226800yxt.4 for ; Wed, 17 Aug 2011 13:49:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=2tUt0mDD0o3dSTeozUIC0O8oWUWBBSOdKyvVsqYJuBw=; b=N3ovCcAzqpMHMzFJ/VXrGOIVwWv9OKfR4qJUE4GFbM6k24NS4b+CycJ+clKrBn7Kap quaFh8S9CXVNtNwJ5CgSZVNh6X5mS61q7GjsUUy0hAdDQgg45xh5Hic71M73mu2TsTFs AAyjVqX9qNYS2N43sgzTOuV4EPu4L394OXCso= Received: by 10.236.9.41 with SMTP id 29mr4645319yhs.212.1313614167552; Wed, 17 Aug 2011 13:49:27 -0700 (PDT) Received: from localhost.localdomain (betelgeuse.cs.uchicago.edu [128.135.24.226]) by mx.google.com with ESMTPS id a29sm1237029yhj.59.2011.08.17.13.49.26 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 17 Aug 2011 13:49:26 -0700 (PDT) From: Bryce Lanham To: qemu-devel@nongnu.org Date: Wed, 17 Aug 2011 15:46:47 -0500 Message-Id: <1313614076-28878-43-git-send-email-blanham@gmail.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1313614076-28878-1-git-send-email-blanham@gmail.com> References: <1313614076-28878-1-git-send-email-blanham@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 209.85.213.173 Cc: Laurent Vivier Subject: [Qemu-devel] [PATCH 042/111] m68k: set X flag according size of operand Set X flag correctly for addsub, arith_im, addsubq. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Laurent Vivier Signed-off-by: Laurent Vivier --- target-m68k/helper.c | 12 +++++++++++- target-m68k/helpers.h | 4 +++- target-m68k/translate.c | 23 ++++++++++++++++------- 3 files changed, 30 insertions(+), 9 deletions(-) diff --git a/target-m68k/helper.c b/target-m68k/helper.c index 0fa59c8..451b02a 100644 --- a/target-m68k/helper.c +++ b/target-m68k/helper.c @@ -619,7 +619,17 @@ uint32_t HELPER(addx_cc)(CPUState *env, uint32_t op1, uint32_t op2) return res; } -uint32_t HELPER(xflag_lt)(uint32_t a, uint32_t b) +uint32_t HELPER(xflag_lt_i8)(uint32_t a, uint32_t b) +{ + return (uint8_t)a < (uint8_t)b; +} + +uint32_t HELPER(xflag_lt_i16)(uint32_t a, uint32_t b) +{ + return (uint16_t)a < (uint16_t)b; +} + +uint32_t HELPER(xflag_lt_i32)(uint32_t a, uint32_t b) { return a < b; } diff --git a/target-m68k/helpers.h b/target-m68k/helpers.h index 76d3063..2e5b8f8 100644 --- a/target-m68k/helpers.h +++ b/target-m68k/helpers.h @@ -37,7 +37,9 @@ DEF_HELPER_3(roxr32_cc, i32, env, i32, i32) DEF_HELPER_3(roxl8_cc, i32, env, i32, i32) DEF_HELPER_3(roxl16_cc, i32, env, i32, i32) DEF_HELPER_3(roxl32_cc, i32, env, i32, i32) -DEF_HELPER_2(xflag_lt, i32, i32, i32) +DEF_HELPER_2(xflag_lt_i8, i32, i32, i32) +DEF_HELPER_2(xflag_lt_i16, i32, i32, i32) +DEF_HELPER_2(xflag_lt_i32, i32, i32, i32) DEF_HELPER_2(set_sr, void, env, i32) DEF_HELPER_3(movec, void, env, i32, i32) diff --git a/target-m68k/translate.c b/target-m68k/translate.c index 56000eb..f743fd2 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -440,6 +440,15 @@ static inline void gen_flush_flags(DisasContext *s) } \ } while (0) +#define SET_X_FLAG(opsize, a, b) do { \ + switch (opsize) { \ + case OS_BYTE: gen_helper_xflag_lt_i8(QREG_CC_X, a, b); break; \ + case OS_WORD: gen_helper_xflag_lt_i16(QREG_CC_X, a, b); break; \ + case OS_LONG: gen_helper_xflag_lt_i32(QREG_CC_X, a, b); break; \ + default: abort(); \ + } \ +} while (0) + static void gen_logic_cc(DisasContext *s, TCGv val, int opsize) { tcg_gen_mov_i32(QREG_CC_DEST, val); @@ -1160,10 +1169,10 @@ DISAS_INSN(addsub) } if (add) { tcg_gen_add_i32(dest, tmp, src); - gen_helper_xflag_lt(QREG_CC_X, dest, src); + SET_X_FLAG(opsize, dest, src); SET_CC_OP(opsize, ADD); } else { - gen_helper_xflag_lt(QREG_CC_X, tmp, src); + SET_X_FLAG(opsize, tmp, src); tcg_gen_sub_i32(dest, tmp, src); SET_CC_OP(opsize, SUB); } @@ -1413,7 +1422,7 @@ DISAS_INSN(arith_im) break; case 2: /* subi */ tcg_gen_mov_i32(dest, src1); - gen_helper_xflag_lt(QREG_CC_X, dest, tcg_const_i32(im)); + SET_X_FLAG(opsize, dest, tcg_const_i32(im)); tcg_gen_subi_i32(dest, dest, im); gen_update_cc_add(dest, tcg_const_i32(im)); SET_CC_OP(opsize, SUB); @@ -1422,7 +1431,7 @@ DISAS_INSN(arith_im) tcg_gen_mov_i32(dest, src1); tcg_gen_addi_i32(dest, dest, im); gen_update_cc_add(dest, tcg_const_i32(im)); - gen_helper_xflag_lt(QREG_CC_X, dest, tcg_const_i32(im)); + SET_X_FLAG(opsize, dest, tcg_const_i32(im)); SET_CC_OP(opsize, ADD); break; case 5: /* eori */ @@ -1625,7 +1634,7 @@ DISAS_INSN(neg) DEST_EA(insn, opsize, dest, &addr); SET_CC_OP(opsize, SUB); gen_update_cc_add(dest, src1); - gen_helper_xflag_lt(QREG_CC_X, tcg_const_i32(0), dest); + SET_X_FLAG(opsize, tcg_const_i32(0), dest); } static void gen_set_sr_im(DisasContext *s, uint16_t val, int ccr_only) @@ -1920,12 +1929,12 @@ DISAS_INSN(addsubq) } else { src2 = tcg_const_i32(val); if (insn & 0x0100) { - gen_helper_xflag_lt(QREG_CC_X, dest, src2); + SET_X_FLAG(opsize, dest, src2); tcg_gen_subi_i32(dest, dest, val); SET_CC_OP(opsize, SUB); } else { tcg_gen_addi_i32(dest, dest, val); - gen_helper_xflag_lt(QREG_CC_X, dest, src2); + SET_X_FLAG(opsize, dest, src2); SET_CC_OP(opsize, ADD); } gen_update_cc_add(dest, src2);