Patchwork [U-Boot,v3] armv7:cache: D cache line size read method

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Submitter Łukasz Majewski
Date Aug. 17, 2011, 8:51 a.m.
Message ID <1313571104-18493-1-git-send-email-l.majewski@samsung.com>
Download mbox | patch
Permalink /patch/110297/
State Superseded
Headers show

Comments

Łukasz Majewski - Aug. 17, 2011, 8:51 a.m.
This commit adds support for reading the D cache line size for armv7
architecture.

The get_dcache_line_size() function is supposed to work in conjunction
with memalign call to provide D cache aligned DMA buffers.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
CC: Aneesh V <aneesh@ti.com>
CC: Albert ARIBAUD <albert.u.boot@aribaud.net>
---
Changes for v2:
- Weak function get_dcache_line_size added to lib/cache.c for non armv7
architectures
Changes for v3:
- __BIGGEST_ALIGNMENT__ GCC constant added
---
 arch/arm/cpu/armv7/cache_v7.c |   14 ++++++++++++++
 arch/arm/lib/cache.c          |   13 +++++++++++++
 include/common.h              |    1 +
 3 files changed, 28 insertions(+), 0 deletions(-)
Albert ARIBAUD - Aug. 17, 2011, 4:28 p.m.
Hi Lukasz,

Le 17/08/2011 10:51, Lukasz Majewski a écrit :
> This commit adds support for reading the D cache line size for armv7
> architecture.
>
> The get_dcache_line_size() function is supposed to work in conjunction
> with memalign call to provide D cache aligned DMA buffers.
>
> Signed-off-by: Lukasz Majewski<l.majewski@samsung.com>
> Signed-off-by: Kyungmin Park<kyungmin.park@samsung.com>
> CC: Aneesh V<aneesh@ti.com>
> CC: Albert ARIBAUD<albert.u.boot@aribaud.net>
> ---
> Changes for v2:
> - Weak function get_dcache_line_size added to lib/cache.c for non armv7
> architectures
> Changes for v3:
> - __BIGGEST_ALIGNMENT__ GCC constant added
> ---
>   arch/arm/cpu/armv7/cache_v7.c |   14 ++++++++++++++
>   arch/arm/lib/cache.c          |   13 +++++++++++++
>   include/common.h              |    1 +
>   3 files changed, 28 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c
> index 3e1e1bf..ea5a3e4 100644
> --- a/arch/arm/cpu/armv7/cache_v7.c
> +++ b/arch/arm/cpu/armv7/cache_v7.c
> @@ -246,6 +246,20 @@ static void v7_inval_tlb(void)
>   	CP15ISB;
>   }
>
> +/* Read the cache line size (in bytes) */
> +int get_dcache_line_size(void)
> +{
> +	u32 ccsidr, log2_line_len;
> +
> +	ccsidr = get_ccsidr();
> +	log2_line_len = ((ccsidr&  CCSIDR_LINE_SIZE_MASK)>>
> +				CCSIDR_LINE_SIZE_OFFSET) + 2;
> +	/* Converting from words to bytes */
> +	log2_line_len += 2;
> +
> +	return 1<<  log2_line_len;
> +}
> +
>   void invalidate_dcache_all(void)
>   {
>   	v7_maint_dcache_all(ARMV7_DCACHE_INVAL_ALL);
> diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
> index 92b61a2..305f070 100644
> --- a/arch/arm/lib/cache.c
> +++ b/arch/arm/lib/cache.c
> @@ -53,3 +53,16 @@ void	__flush_dcache_all(void)
>   }
>   void	flush_dcache_all(void)
>   	__attribute__((weak, alias("__flush_dcache_all")));
> +
> +/* Default implementation: */
> +/* Read the default D CACHE LINE size */
> +int __attribute__((weak)) get_dcache_line_size(void)
> +{
> +#if defined(CONFIG_SYS_CACHE_LINE_SIZE)&&  !defined(CONFIG_SYS_DCACHE_OFF)
> +	return CONFIG_SYS_CACHE_LINE_SIZE;
> +#else
> +	/* The smallest alignment */
> +	/* for memalign() is 8 Bytes. */
> +	return __BIGGEST_ALIGNMENT__;  /* Constant defined by GCC compiler */

Fix the comment (still says 8 bytes, but that does not fit any more with 
the use of __BIGGEST_ALIGNMENT__).

> +#endif
> +}
> diff --git a/include/common.h b/include/common.h
> index 12a1074..b535300 100644
> --- a/include/common.h
> +++ b/include/common.h
> @@ -622,6 +622,7 @@ void	flush_dcache_range(unsigned long start, unsigned long stop);
>   void	invalidate_dcache_range(unsigned long start, unsigned long stop);
>   void	invalidate_dcache_all(void);
>   void	invalidate_icache_all(void);
> +int     get_dcache_line_size(void);
>
>   /* arch/$(ARCH)/lib/ticks.S */
>   unsigned long long get_ticks(void);

Amicalement,

Patch

diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c
index 3e1e1bf..ea5a3e4 100644
--- a/arch/arm/cpu/armv7/cache_v7.c
+++ b/arch/arm/cpu/armv7/cache_v7.c
@@ -246,6 +246,20 @@  static void v7_inval_tlb(void)
 	CP15ISB;
 }
 
+/* Read the cache line size (in bytes) */
+int get_dcache_line_size(void)
+{
+	u32 ccsidr, log2_line_len;
+
+	ccsidr = get_ccsidr();
+	log2_line_len = ((ccsidr & CCSIDR_LINE_SIZE_MASK) >>
+				CCSIDR_LINE_SIZE_OFFSET) + 2;
+	/* Converting from words to bytes */
+	log2_line_len += 2;
+
+	return 1 << log2_line_len;
+}
+
 void invalidate_dcache_all(void)
 {
 	v7_maint_dcache_all(ARMV7_DCACHE_INVAL_ALL);
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
index 92b61a2..305f070 100644
--- a/arch/arm/lib/cache.c
+++ b/arch/arm/lib/cache.c
@@ -53,3 +53,16 @@  void	__flush_dcache_all(void)
 }
 void	flush_dcache_all(void)
 	__attribute__((weak, alias("__flush_dcache_all")));
+
+/* Default implementation: */
+/* Read the default D CACHE LINE size */
+int __attribute__((weak)) get_dcache_line_size(void)
+{
+#if defined(CONFIG_SYS_CACHE_LINE_SIZE) && !defined(CONFIG_SYS_DCACHE_OFF)
+	return CONFIG_SYS_CACHE_LINE_SIZE;
+#else
+	/* The smallest alignment */
+	/* for memalign() is 8 Bytes. */
+	return __BIGGEST_ALIGNMENT__;  /* Constant defined by GCC compiler */
+#endif
+}
diff --git a/include/common.h b/include/common.h
index 12a1074..b535300 100644
--- a/include/common.h
+++ b/include/common.h
@@ -622,6 +622,7 @@  void	flush_dcache_range(unsigned long start, unsigned long stop);
 void	invalidate_dcache_range(unsigned long start, unsigned long stop);
 void	invalidate_dcache_all(void);
 void	invalidate_icache_all(void);
+int     get_dcache_line_size(void);
 
 /* arch/$(ARCH)/lib/ticks.S */
 unsigned long long get_ticks(void);