Patchwork [U-Boot,v4,1/4] arm: do not force d-cache enable on all boards

login
register
mail settings
Submitter Aneesh V
Date Aug. 16, 2011, 2:33 p.m.
Message ID <1313505185-21514-1-git-send-email-aneesh@ti.com>
Download mbox | patch
Permalink /patch/110188/
State Accepted
Commit cba4b1809f043bf85c806e5a4e342f62bd5ded45
Delegated to: Albert ARIBAUD
Headers show

Comments

Aneesh V - Aug. 16, 2011, 2:33 p.m.
c2dd0d45540397704de9b13287417d21049d34c6 added dcache_enable()
to board_init_r(). This enables d-cache for all ARM boards.
As a result some of the arm boards that are not cache-ready
are broken. Revert this change and allow platform code to
take the decision on d-cache enabling.

Also add some documentation for cache usage in ARM.

Signed-off-by: Aneesh V <aneesh@ti.com>
---
V2:
* Updated with additional guidelines in the README.

V3:
* No change

V4:
* Fix typo in README
---
 arch/arm/lib/board.c  |    8 ++----
 arch/arm/lib/cache.c  |   12 +++++++++++
 doc/README.arm-caches |   51 +++++++++++++++++++++++++++++++++++++++++++++++++
 include/common.h      |    1 +
 4 files changed, 67 insertions(+), 5 deletions(-)
 create mode 100644 doc/README.arm-caches

Patch

diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c
index 14a56f6..38a31d8 100644
--- a/arch/arm/lib/board.c
+++ b/arch/arm/lib/board.c
@@ -451,11 +451,9 @@  void board_init_r(gd_t *id, ulong dest_addr)
 	gd->flags |= GD_FLG_RELOC;	/* tell others: relocation done */
 
 	monitor_flash_len = _end_ofs;
-	/*
-	 * Enable D$:
-	 * I$, if needed, must be already enabled in start.S
-	 */
-	dcache_enable();
+
+	/* Enable caches */
+	enable_caches();
 
 	debug("monitor flash len: %08lX\n", monitor_flash_len);
 	board_init();	/* Setup chipselects */
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
index 92b61a2..b545fb7 100644
--- a/arch/arm/lib/cache.c
+++ b/arch/arm/lib/cache.c
@@ -53,3 +53,15 @@  void	__flush_dcache_all(void)
 }
 void	flush_dcache_all(void)
 	__attribute__((weak, alias("__flush_dcache_all")));
+
+
+/*
+ * Default implementation of enable_caches()
+ * Real implementation should be in platform code
+ */
+void __enable_caches(void)
+{
+	puts("WARNING: Caches not enabled\n");
+}
+void enable_caches(void)
+	__attribute__((weak, alias("__enable_caches")));
diff --git a/doc/README.arm-caches b/doc/README.arm-caches
new file mode 100644
index 0000000..cd2b458
--- /dev/null
+++ b/doc/README.arm-caches
@@ -0,0 +1,51 @@ 
+Disabling I-cache:
+- Set CONFIG_SYS_ICACHE_OFF
+
+Disabling D-cache:
+- Set CONFIG_SYS_DCACHE_OFF
+
+Enabling I-cache:
+- Make sure CONFIG_SYS_ICACHE_OFF is not set and call icache_enable().
+
+Enabling D-cache:
+- Make sure CONFIG_SYS_DCACHE_OFF is not set and call dcache_enable().
+
+Enabling Caches at System Startup:
+- Implement enable_caches() for your platform and enable the I-cache and
+  D-cache from this function. This function is called immediately
+  after relocation.
+
+Guidelines for Working with D-cache:
+
+Memory to Peripheral DMA:
+- Flush the buffer after the MPU writes the data and before the DMA is
+  initiated.
+
+Peripheral to Memory DMA:
+- Invalidate the buffer before starting the DMA. In case there are any dirty
+  lines from the DMA buffer in the cache, subsequent cache-line replacements
+  may corrupt the buffer in memory while the DMA is still going on. Cache-line
+  replacement can happen if the CPU tries to bring some other memory locations
+  into the cache while the DMA is going on.
+- Invalidate the buffer after the DMA is complete and before the MPU reads
+  it. This may be needed in addition to the invalidation before the DMA
+  mentioned above, because in some processors memory contents can spontaneously
+  come to the cache due to speculative memory access by the CPU. If this
+  happens with the DMA buffer while DMA is going on we have a coherency problem.
+
+Buffer Requirements:
+- Any buffer that is invalidated(that is, typically the peripheral to
+  memory DMA buffer) should be aligned to cache-line boundary both at
+  at the beginning and at the end of the buffer.
+- If the buffer is not cache-line aligned invalidation will be restricted
+  to the aligned part. That is, one cache-line at the respective boundary
+  may be left out while doing invalidation.
+
+Cleanup Before Linux:
+- cleanup_before_linux() should flush the D-cache, invalidate I-cache, and
+  disable MMU and caches.
+- The following sequence is advisable while disabling d-cache:
+  1. disable_dcache() - flushes and disables d-cache
+  2. invalidate_dcache_all() - invalid any entry that came to the cache
+	in the short period after the cache was flushed but before the
+	cache got disabled.
diff --git a/include/common.h b/include/common.h
index 12a1074..bd10f31 100644
--- a/include/common.h
+++ b/include/common.h
@@ -616,6 +616,7 @@  ulong	lcd_setmem (ulong);
 ulong	video_setmem (ulong);
 
 /* arch/$(ARCH)/lib/cache.c */
+void	enable_caches(void);
 void	flush_cache   (unsigned long, unsigned long);
 void	flush_dcache_all(void);
 void	flush_dcache_range(unsigned long start, unsigned long stop);