@@ -246,6 +246,20 @@ static void v7_inval_tlb(void)
CP15ISB;
}
+/* Read the cache line size (in bytes) */
+int get_dcache_line_size(void)
+{
+ u32 ccsidr, log2_line_len;
+
+ ccsidr = get_ccsidr();
+ log2_line_len = ((ccsidr & CCSIDR_LINE_SIZE_MASK) >>
+ CCSIDR_LINE_SIZE_OFFSET) + 2;
+ /* Converting from words to bytes */
+ log2_line_len += 2;
+
+ return 1 << log2_line_len;
+}
+
void invalidate_dcache_all(void)
{
v7_maint_dcache_all(ARMV7_DCACHE_INVAL_ALL);
@@ -53,3 +53,14 @@ void __flush_dcache_all(void)
}
void flush_dcache_all(void)
__attribute__((weak, alias("__flush_dcache_all")));
+
+/* Default implementation: */
+/* Read the default D CACHE LINE size */
+int __attribute__((weak)) get_dcache_line_size(void)
+{
+#if defined(CONFIG_SYS_CACHE_LINE_SIZE) && !defined(CONFIG_SYS_DCACHE_OFF)
+ return CONFIG_SYS_CACHE_LINE_SIZE;
+#else
+ return 8; /* Default alignment for memalign() */
+#endif
+}
@@ -622,6 +622,7 @@ void flush_dcache_range(unsigned long start, unsigned long stop);
void invalidate_dcache_range(unsigned long start, unsigned long stop);
void invalidate_dcache_all(void);
void invalidate_icache_all(void);
+int get_dcache_line_size(void);
/* arch/$(ARCH)/lib/ticks.S */
unsigned long long get_ticks(void);