@@ -145,12 +145,6 @@ (define_memory_constraint "wF"
"Memory operand suitable for power8 GPR load fusion"
(match_operand 0 "fusion_addis_mem_combo_load"))
-(define_register_constraint "wH" "rs6000_constraints[RS6000_CONSTRAINT_wH]"
- "Altivec register to hold 32-bit integers or NO_REGS.")
-
-(define_register_constraint "wI" "rs6000_constraints[RS6000_CONSTRAINT_wI]"
- "FPR register to hold 32-bit integers or NO_REGS.")
-
(define_constraint "wL"
"Int constant that is the element number mfvsrld accesses in a vector."
(and (match_code "const_int")
@@ -2528,8 +2528,6 @@ rs6000_debug_reg_global (void)
"wx reg_class = %s\n"
"wz reg_class = %s\n"
"wA reg_class = %s\n"
- "wH reg_class = %s\n"
- "wI reg_class = %s\n"
"\n",
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_d]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_f]],
@@ -2554,9 +2552,7 @@ rs6000_debug_reg_global (void)
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ww]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wx]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wz]],
- reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wA]],
- reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wH]],
- reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wI]]);
+ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wA]]);
nl = "\n";
for (m = 0; m < NUM_MACHINE_MODES; ++m)
@@ -3180,9 +3176,7 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
wv - Altivec register for ISA 2.06 VSX DF/DI load/stores.
ww - Register class to do SF conversions in with VSX operations.
wx - Float register if we can do 32-bit int stores.
- wz - Float register if we can do 32-bit unsigned int loads.
- wH - Altivec register if SImode is allowed in VSX registers.
- wI - Float register if SImode is allowed in VSX registers. */
+ wz - Float register if we can do 32-bit unsigned int loads. */
if (TARGET_HARD_FLOAT)
{
@@ -3250,13 +3244,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
if (TARGET_DIRECT_MOVE_128)
rs6000_constraints[RS6000_CONSTRAINT_we] = VSX_REGS;
- /* Support small integers in VSX registers. */
- if (TARGET_P8_VECTOR)
- {
- rs6000_constraints[RS6000_CONSTRAINT_wH] = ALTIVEC_REGS;
- rs6000_constraints[RS6000_CONSTRAINT_wI] = FLOAT_REGS;
- }
-
/* Set up the reload helper and direct move functions. */
if (TARGET_VSX || TARGET_ALTIVEC)
{
@@ -1269,8 +1269,6 @@ enum r6000_reg_class_enum {
RS6000_CONSTRAINT_wx, /* FPR register for STFIWX */
RS6000_CONSTRAINT_wz, /* FPR register for LFIWZX */
RS6000_CONSTRAINT_wA, /* BASE_REGS if 64-bit. */
- RS6000_CONSTRAINT_wH, /* Altivec register for 32-bit integers. */
- RS6000_CONSTRAINT_wI, /* VSX register for 32-bit integers. */
RS6000_CONSTRAINT_MAX
};
@@ -726,8 +726,8 @@ (define_mode_iterator ALTIVEC_DFORM [DF
;; complex forms. Basic data transfer is done later.
(define_insn "zero_extendqi<mode>2"
- [(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,r,^wIwH,^wH")
- (zero_extend:EXTQI (match_operand:QI 1 "reg_or_mem_operand" "m,r,Z,wH")))]
+ [(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,r,^wa,^v")
+ (zero_extend:EXTQI (match_operand:QI 1 "reg_or_mem_operand" "m,r,Z,v")))]
""
"@
lbz%U1%X1 %0,%1
@@ -780,8 +780,8 @@ (define_insn_and_split "*zero_extendqi<mode>2_dot2"
(define_insn "zero_extendhi<mode>2"
- [(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r,^wIwH,^wH")
- (zero_extend:EXTHI (match_operand:HI 1 "reg_or_mem_operand" "m,r,Z,wH")))]
+ [(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r,^wa,^v")
+ (zero_extend:EXTHI (match_operand:HI 1 "reg_or_mem_operand" "m,r,Z,v")))]
""
"@
lhz%U1%X1 %0,%1
@@ -834,8 +834,8 @@ (define_insn_and_split "*zero_extendhi<mode>2_dot2"
(define_insn "zero_extendsi<mode>2"
- [(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r,wz,wa,wj,r,wIwH")
- (zero_extend:EXTSI (match_operand:SI 1 "reg_or_mem_operand" "m,r,Z,Z,r,wIwH,wIwH")))]
+ [(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r,wz,wa,wj,r,wa")
+ (zero_extend:EXTSI (match_operand:SI 1 "reg_or_mem_operand" "m,r,Z,Z,r,wa,wa")))]
""
"@
lwz%U1%X1 %0,%1
@@ -846,7 +846,7 @@ (define_insn "zero_extendsi<mode>2"
mfvsrwz %0,%x1
xxextractuw %x0,%x1,4"
[(set_attr "type" "load,shift,fpload,fpload,mffgpr,mftgpr,vecexts")
- (set_attr "isa" "*,*,*,p8v,*,*,p9v")])
+ (set_attr "isa" "*,*,*,p8v,*,p8v,p9v")])
(define_insn_and_split "*zero_extendsi<mode>2_dot"
[(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
@@ -891,8 +891,8 @@ (define_insn_and_split "*zero_extendsi<mode>2_dot2"
(define_insn "extendqi<mode>2"
- [(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,?*wH")
- (sign_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,?*wH")))]
+ [(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,?*v")
+ (sign_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,?*v")))]
""
"@
extsb %0,%1
@@ -949,8 +949,8 @@ (define_expand "extendhi<mode>2"
"")
(define_insn "*extendhi<mode>2"
- [(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r,?*wH,?*wH")
- (sign_extend:EXTHI (match_operand:HI 1 "reg_or_mem_operand" "m,r,Z,wH")))]
+ [(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r,?*v,?*v")
+ (sign_extend:EXTHI (match_operand:HI 1 "reg_or_mem_operand" "m,r,Z,v")))]
""
"@
lha%U1%X1 %0,%1
@@ -1019,9 +1019,9 @@ (define_insn_and_split "*extendhi<mode>2_dot2"
(define_insn "extendsi<mode>2"
[(set (match_operand:EXTSI 0 "gpc_reg_operand"
- "=r, r, wl, wa, wj, wH, wH, wr")
+ "=r, r, wl, wa, wj, v, v, wr")
(sign_extend:EXTSI (match_operand:SI 1 "lwa_operand"
- "YZ, r, Z, Z, r, wH, wH, ?wIwH")))]
+ "YZ, r, Z, Z, r, v, v, ?wa")))]
""
"@
lwa%U1%X1 %0,%1
@@ -1035,7 +1035,7 @@ (define_insn "extendsi<mode>2"
[(set_attr "type" "load,exts,fpload,fpload,mffgpr,vecexts,vecperm,mftgpr")
(set_attr "sign_extend" "yes")
(set_attr "length" "4,4,4,4,4,4,8,8")
- (set_attr "isa" "*,*,*,p8v,*,p9v,*,*")])
+ (set_attr "isa" "*,*,*,p8v,*,p9v,p8v,p8v")])
(define_split
[(set (match_operand:EXTSI 0 "int_reg_operand")
@@ -5233,8 +5233,8 @@ (define_insn "*xxsel<mode>"
; We don't define lfiwax/lfiwzx with the normal definition, because we
; don't want to support putting SImode in FPR registers.
(define_insn "lfiwax"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wj,wj,wH")
- (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r,wH")]
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wj,wj,v")
+ (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r,v")]
UNSPEC_LFIWAX))]
"TARGET_HARD_FLOAT && TARGET_LFIWAX"
"@
@@ -5315,8 +5315,8 @@ (define_insn_and_split "floatsi<mode>2_lfiwax_mem"
(set_attr "type" "fpload")])
(define_insn "lfiwzx"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wj,wj,wIwH")
- (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r,wIwH")]
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wj,wj,wa")
+ (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r,wa")]
UNSPEC_LFIWZX))]
"TARGET_HARD_FLOAT && TARGET_LFIWZX"
"@
@@ -5569,10 +5569,10 @@ (define_expand "float<QHI:mode><FP_ISA3:mode>2"
(define_insn_and_split "*float<QHI:mode><FP_ISA3:mode>2_internal"
[(set (match_operand:FP_ISA3 0 "vsx_register_operand" "=<Fv>,<Fv>,<Fv>")
(float:FP_ISA3
- (match_operand:QHI 1 "reg_or_indexed_operand" "wH,r,Z")))
- (clobber (match_scratch:DI 2 "=wH,wi,wH"))
+ (match_operand:QHI 1 "reg_or_indexed_operand" "v,r,Z")))
+ (clobber (match_scratch:DI 2 "=v,wi,v"))
(clobber (match_scratch:DI 3 "=X,r,X"))
- (clobber (match_scratch:<QHI:MODE> 4 "=X,X,wH"))]
+ (clobber (match_scratch:<QHI:MODE> 4 "=X,X,v"))]
"TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64"
"#"
"&& reload_completed"
@@ -5622,8 +5622,8 @@ (define_expand "floatuns<QHI:mode><FP_ISA3:mode>2"
(define_insn_and_split "*floatuns<QHI:mode><FP_ISA3:mode>2_internal"
[(set (match_operand:FP_ISA3 0 "vsx_register_operand" "=<Fv>,<Fv>,<Fv>")
(unsigned_float:FP_ISA3
- (match_operand:QHI 1 "reg_or_indexed_operand" "wH,r,Z")))
- (clobber (match_scratch:DI 2 "=wH,wi,wIwH"))
+ (match_operand:QHI 1 "reg_or_indexed_operand" "v,r,Z")))
+ (clobber (match_scratch:DI 2 "=v,wi,wa"))
(clobber (match_scratch:DI 3 "=X,r,X"))]
"TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64"
"#"
@@ -5764,8 +5764,8 @@ (define_insn "*fix_trunc<mode>di2_fctidz"
;; register allocation prevents the register allocator from doing a direct move
;; of the SImode value to a GPR, and then a store/load.
(define_insn_and_split "fix<uns>_trunc<SFDF:mode><QHI:mode>2"
- [(set (match_operand:<QHI:MODE> 0 "gpc_reg_operand" "=wI,wIwH,r")
- (any_fix:QHI (match_operand:SFDF 1 "gpc_reg_operand" "wI,wIwH,wa")))
+ [(set (match_operand:<QHI:MODE> 0 "gpc_reg_operand" "=d,wa,r")
+ (any_fix:QHI (match_operand:SFDF 1 "gpc_reg_operand" "d,wa,wa")))
(clobber (match_scratch:SI 2 "=X,X,wi"))]
"TARGET_DIRECT_MOVE"
"@
@@ -6892,16 +6892,16 @@ (define_insn "movsi_low"
;; MF%1 MT%0 NOP
(define_insn "*movsi_internal1"
[(set (match_operand:SI 0 "nonimmediate_operand"
- "=r, r, r, wI, wH,
+ "=r, r, r, d, v,
m, Z, Z, r, r,
- r, wIwH, wIwH, wIwH, v,
- wIwH, wH, wH, wIwH, r,
+ r, wa, wa, wa, v,
+ wa, v, v, wa, r,
r, *h, *h")
(match_operand:SI 1 "input_operand"
"r, U, m, Z, Z,
- r, wI, wH, I, L,
- n, wIwH, O, wM, wB,
- O, wM, wS, r, wIwH,
+ r, d, v, I, L,
+ n, wa, O, wM, wB,
+ O, wM, wS, r, wa,
*h, r, 0"))]
"gpc_reg_operand (operands[0], SImode)
|| gpc_reg_operand (operands[1], SImode)"
@@ -6942,10 +6942,10 @@ (define_insn "*movsi_internal1"
4, 4, 8, 4, 4,
4, 4, 4")
(set_attr "isa"
- "*, *, *, *, *,
- *, *, *, *, *,
- *, *, p9v, p9v, p8v,
- p9v, *, p9v, *, *,
+ "*, *, *, p8v, p8v,
+ *, p8v, p8v, *, *,
+ *, p8v, p9v, p9v, p8v,
+ p9v, p8v, p9v, p8v, p8v,
*, *, *")])
;; Like movsi, but adjust a SF value to be used in a SI context, i.e.
@@ -6969,17 +6969,17 @@ (define_insn "*movsi_internal1"
(define_insn_and_split "movsi_from_sf"
[(set (match_operand:SI 0 "nonimmediate_operand"
- "=r, r, ?*wI, ?*wH, m,
- m, wY, Z, r, ?*wIwH,
- wIwH")
+ "=r, r, ?*d, ?*v, m,
+ m, wY, Z, r, ?*wa,
+ wa")
(unspec:SI [(match_operand:SF 1 "input_operand"
"r, m, Z, Z, r,
- f, v, wa, wIwH, wIwH,
+ f, v, wa, wa, wa,
r")]
UNSPEC_SI_FROM_SF))
(clobber (match_scratch:V4SF 2
"=X, X, X, X, X,
- X, X, X, wIwH, X,
+ X, X, X, wa, X,
X"))]
"TARGET_NO_SF_SUBREG
&& (register_operand (operands[0], SImode)
@@ -7020,9 +7020,9 @@ (define_insn_and_split "movsi_from_sf"
4, 4, 4, 8, 4,
4")
(set_attr "isa"
- "*, *, *, *, *,
- *, p9v, p8v, *, *,
- *")])
+ "*, *, p8v, p8v, *,
+ *, p9v, p8v, p8v, p8v,
+ p8v")])
;; movsi_from_sf with zero extension
;;
@@ -7031,16 +7031,16 @@ (define_insn_and_split "movsi_from_sf"
(define_insn_and_split "*movdi_from_sf_zero_ext"
[(set (match_operand:DI 0 "gpc_reg_operand"
- "=r, r, ?*wI, ?*wH, r,
- ?wH, wIwH")
+ "=r, r, ?*d, ?*v, r,
+ ?v, wa")
(zero_extend:DI
(unspec:SI [(match_operand:SF 1 "input_operand"
- "r, m, Z, Z, wIwH,
- wIwH, r")]
+ "r, m, Z, Z, wa,
+ wa, r")]
UNSPEC_SI_FROM_SF)))
(clobber (match_scratch:V4SF 2
"=X, X, X, X, wa,
- wIwH, X"))]
+ wa, X"))]
"TARGET_DIRECT_MOVE_64BIT
&& (register_operand (operands[0], DImode)
|| register_operand (operands[1], SImode))"
@@ -7073,8 +7073,8 @@ (define_insn_and_split "*movdi_from_sf_zero_ext"
"4, 4, 4, 4, 8,
8, 4")
(set_attr "isa"
- "*, *, *, *, *,
- p9v, *")])
+ "*, *, p8v, p8v, p8v,
+ p9v, p8v")])
;; Like movsi_from_sf, but combine a convert from DFmode to SFmode before
;; moving it to SImode. We cannot do a SFmode store without having to do the
@@ -7168,12 +7168,12 @@ (define_expand "mov<mode>"
;; MTVSRWZ MF%1 MT%1 NOP
(define_insn "*mov<mode>_internal"
[(set (match_operand:QHI 0 "nonimmediate_operand"
- "=r, r, wIwH, m, Z, r,
- wIwH, wIwH, wIwH, wH, ?wH, r,
- wIwH, r, *c*l, *h")
+ "=r, r, wa, m, Z, r,
+ wa, wa, wa, v, ?v, r,
+ wa, r, *c*l, *h")
(match_operand:QHI 1 "input_operand"
- "r, m, Z, r, wIwH, i,
- wIwH, O, wM, wB, wS, wIwH,
+ "r, m, Z, r, wa, i,
+ wa, O, wM, wB, wS, wa,
r, *h, r, 0"))]
"gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode)"
@@ -8705,7 +8705,7 @@ (define_insn_and_split "reload_gpr_from_vsxsf"
[(set (match_operand:SF 0 "register_operand" "=r")
(unspec:SF [(match_operand:SF 1 "register_operand" "ww")]
UNSPEC_P8V_RELOAD_FROM_VSX))
- (clobber (match_operand:V4SF 2 "register_operand" "=wIwH"))]
+ (clobber (match_operand:V4SF 2 "register_operand" "=wa"))]
"TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
"#"
"&& reload_completed"
@@ -8722,8 +8722,8 @@ (define_insn_and_split "reload_gpr_from_vsxsf"
DONE;
}
[(set_attr "length" "8")
- (set_attr "type" "two")])
-
+ (set_attr "type" "two")
+ (set_attr "isa" "p8v")])
;; Next come the multi-word integer load and store and the load and store
;; multiple insns.
@@ -3525,7 +3525,7 @@ (define_expand "vsx_extract_<mode>"
(define_insn "vsx_extract_<mode>_p9"
[(set (match_operand:<VS_scalar> 0 "gpc_reg_operand" "=r,<VSX_EX>")
(vec_select:<VS_scalar>
- (match_operand:VSX_EXTRACT_I 1 "gpc_reg_operand" "wH,<VSX_EX>")
+ (match_operand:VSX_EXTRACT_I 1 "gpc_reg_operand" "v,<VSX_EX>")
(parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n,n")])))
(clobber (match_scratch:SI 3 "=r,X"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_VEXTRACTUB"
@@ -3581,7 +3581,7 @@ (define_insn_and_split "*vsx_extract_<mode>_di_p9"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,<VSX_EX>")
(zero_extend:DI
(vec_select:<VS_scalar>
- (match_operand:VSX_EXTRACT_I 1 "gpc_reg_operand" "wH,<VSX_EX>")
+ (match_operand:VSX_EXTRACT_I 1 "gpc_reg_operand" "v,<VSX_EX>")
(parallel [(match_operand:QI 2 "const_int_operand" "n,n")]))))
(clobber (match_scratch:SI 3 "=r,X"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_VEXTRACTUB"
@@ -3617,7 +3617,7 @@ (define_insn_and_split "*vsx_extract_<mode>_store_p9"
(match_dup 3))])
(define_insn_and_split "*vsx_extract_si"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=r,wHwI,Z")
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r,wa,Z")
(vec_select:SI
(match_operand:V4SI 1 "gpc_reg_operand" "v,v,v")
(parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n,n")])))
@@ -3664,7 +3664,8 @@ (define_insn_and_split "*vsx_extract_si"
DONE;
}
[(set_attr "type" "mftgpr,vecperm,fpstore")
- (set_attr "length" "8")])
+ (set_attr "length" "8")
+ (set_attr "isa" "*,p8v,*")])
(define_insn_and_split "*vsx_extract_<mode>_p8"
[(set (match_operand:<VS_scalar> 0 "nonimmediate_operand" "=r")
@@ -3735,7 +3736,7 @@ (define_insn_and_split "*vsx_extract_<mode>_load"
(define_insn_and_split "vsx_extract_<mode>_var"
[(set (match_operand:<VS_scalar> 0 "gpc_reg_operand" "=r,r,r")
(unspec:<VS_scalar>
- [(match_operand:VSX_EXTRACT_I 1 "input_operand" "wH,v,m")
+ [(match_operand:VSX_EXTRACT_I 1 "input_operand" "v,v,m")
(match_operand:DI 2 "gpc_reg_operand" "r,r,r")]
UNSPEC_VSX_EXTRACT))
(clobber (match_scratch:DI 3 "=r,r,&b"))
@@ -3755,7 +3756,7 @@ (define_insn_and_split "*vsx_extract_<mode>_<VS_scalar>mode_var"
[(set (match_operand:<VS_scalar> 0 "gpc_reg_operand" "=r,r,r")
(zero_extend:<VS_scalar>
(unspec:<VSX_EXTRACT_I:VS_scalar>
- [(match_operand:VSX_EXTRACT_I 1 "input_operand" "wH,v,m")
+ [(match_operand:VSX_EXTRACT_I 1 "input_operand" "v,v,m")
(match_operand:DI 2 "gpc_reg_operand" "r,r,r")]
UNSPEC_VSX_EXTRACT)))
(clobber (match_scratch:DI 3 "=r,r,&b"))
@@ -3955,7 +3956,7 @@ (define_insn_and_split "vsx_set_v4sf_p9"
(match_operand:SF 2 "gpc_reg_operand" "ww")
(match_operand:QI 3 "const_0_to_3_operand" "n")]
UNSPEC_VSX_SET))
- (clobber (match_scratch:SI 4 "=&wIwH"))]
+ (clobber (match_scratch:SI 4 "=&wa"))]
"VECTOR_MEM_VSX_P (V4SFmode) && TARGET_P9_VECTOR && TARGET_POWERPC64"
"#"
"&& reload_completed"
@@ -3991,7 +3992,7 @@ (define_insn_and_split "*vsx_set_v4sf_p9_zero"
(match_operand:SF 2 "zero_fp_constant" "j")
(match_operand:QI 3 "const_0_to_3_operand" "n")]
UNSPEC_VSX_SET))
- (clobber (match_scratch:SI 4 "=&wIwH"))]
+ (clobber (match_scratch:SI 4 "=&wa"))]
"VECTOR_MEM_VSX_P (V4SFmode) && TARGET_P9_VECTOR && TARGET_POWERPC64"
"#"
"&& reload_completed"
@@ -4049,7 +4050,7 @@ (define_insn_and_split "*vsx_insert_extract_v4sf_p9_2"
[(match_operand:QI 3 "const_0_to_3_operand" "n")]))
(match_operand:QI 4 "const_0_to_3_operand" "n")]
UNSPEC_VSX_SET))
- (clobber (match_scratch:SI 5 "=&wIwH"))]
+ (clobber (match_scratch:SI 5 "=&wa"))]
"VECTOR_MEM_VSX_P (V4SFmode) && VECTOR_MEM_VSX_P (V4SImode)
&& TARGET_P9_VECTOR && TARGET_POWERPC64
&& (INTVAL (operands[3]) != (BYTES_BIG_ENDIAN ? 1 : 2))"
@@ -3325,12 +3325,6 @@ Memory operand suitable for power8 GPR load fusion
@item wG
Memory operand suitable for TOC fusion memory references.
-@item wH
-Altivec register if @option{-mvsx-small-integer}.
-
-@item wI
-Floating point register if @option{-mvsx-small-integer}.
-
@item wL
Int constant that is the element number that the MFVSRLD instruction.
targets.