| Message ID | 20190516215955.10000-1-hjl.tools@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | i386: Enable MMX intrinsics without SSE/SSE2/SSSE3 | expand |
On Thu, May 16, 2019 at 11:59 PM H.J. Lu <hjl.tools@gmail.com> wrote: > > Since MMX intrinsics are marked with SSE/SSE2/SSSE3 for SSE emulation, > enable them without SSE/SSE2/SSSE3 if MMX is enabled. > > Restore TARGET_3DNOW check, which was changed to TARGET_3DNOW_A by > revision 271235. > > gcc/ > > PR target/90497 > * config/i386/i386-expand.c (ix86_expand_builtin): Enable MMX > intrinsics without SSE/SSE2/SSSE3. > * config/i386/mmx.md (mmx_uavgv8qi3): Restore TARGET_3DNOW > check. > (*mmx_uavgv8qi3): Likewise. OK with a small nit. Thanks, Uros. > > gcc/testsuite/ > > PR target/90497 > * gcc.target/i386/pr90497-1.c: New test. > * gcc.target/i386/pr90497-2.c: Likewise. > --- > gcc/config/i386/i386-expand.c | 6 ++++-- > gcc/config/i386/mmx.md | 4 ++-- > gcc/testsuite/gcc.target/i386/pr90497-1.c | 12 ++++++++++++ > gcc/testsuite/gcc.target/i386/pr90497-2.c | 11 +++++++++++ > 4 files changed, 29 insertions(+), 4 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/i386/pr90497-1.c > create mode 100644 gcc/testsuite/gcc.target/i386/pr90497-2.c > > diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c > index df035607fa7..35aadefdef3 100644 > --- a/gcc/config/i386/i386-expand.c > +++ b/gcc/config/i386/i386-expand.c > @@ -10937,8 +10937,10 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget, > && (isa & (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4)) != 0) > isa |= (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4); > /* Use SSE/SSE2/SSSE3 to emulate MMX intrinsics in 64-bit mode when > - MMX is disabled. */ > - if (TARGET_MMX_WITH_SSE) > + MMX is disabled. NB: Since MMX intrinsics are marked with > + SSE/SSE2/SSSE3, enable them without SSE/SSE2/SSSE3 if MMX is > + enabled. */ > + if (TARGET_MMX_WITH_SSE || TARGET_MMX) Please use "TARGET_MMX || TARGET_MMX_WITH_SSE" as is the case with all these conditions. > { > if (((bisa & (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX)) > == (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX)) > diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md > index 29bcf931836..adad950fa04 100644 > --- a/gcc/config/i386/mmx.md > +++ b/gcc/config/i386/mmx.md > @@ -1745,7 +1745,7 @@ > (const_int 1) (const_int 1)])) > (const_int 1))))] > "(TARGET_MMX || TARGET_MMX_WITH_SSE) > - && (TARGET_SSE || TARGET_3DNOW_A)" > + && (TARGET_SSE || TARGET_3DNOW)" > "ix86_fixup_binary_operands_no_copy (PLUS, V8QImode, operands);") > > (define_insn "*mmx_uavgv8qi3" > @@ -1764,7 +1764,7 @@ > (const_int 1) (const_int 1)])) > (const_int 1))))] > "(TARGET_MMX || TARGET_MMX_WITH_SSE) > - && (TARGET_SSE || TARGET_3DNOW_A) > + && (TARGET_SSE || TARGET_3DNOW) > && ix86_binary_operator_ok (PLUS, V8QImode, operands)" > { > /* These two instructions have the same operation, but their encoding > diff --git a/gcc/testsuite/gcc.target/i386/pr90497-1.c b/gcc/testsuite/gcc.target/i386/pr90497-1.c > new file mode 100644 > index 00000000000..ed6ded7efbc > --- /dev/null > +++ b/gcc/testsuite/gcc.target/i386/pr90497-1.c > @@ -0,0 +1,12 @@ > +/* PR target/90497 */ > +/* { dg-do compile } */ > +/* { dg-options "-mno-sse -mmmx" { target ia32 } } */ > +/* { dg-options "-mno-mmx" { target { ! ia32 } } } */ > + > +typedef char __v8qi __attribute__ ((__vector_size__ (8))); > + > +__v8qi > +foo (__v8qi x, __v8qi y) > +{ > + return __builtin_ia32_pcmpeqb (x, y); > +} > diff --git a/gcc/testsuite/gcc.target/i386/pr90497-2.c b/gcc/testsuite/gcc.target/i386/pr90497-2.c > new file mode 100644 > index 00000000000..99ee5756b76 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/i386/pr90497-2.c > @@ -0,0 +1,11 @@ > +/* PR target/90497 */ > +/* { dg-do compile { target ia32 } } */ > +/* { dg-options "-mno-sse -m3dnow" } */ > + > +typedef char __v8qi __attribute__ ((__vector_size__ (8))); > + > +__v8qi > +foo (__v8qi x, __v8qi y) > +{ > + return __builtin_ia32_pavgusb (x, y); > +} > -- > 2.20.1 >
On Thu, May 16, 2019 at 11:21 PM Uros Bizjak <ubizjak@gmail.com> wrote: > > On Thu, May 16, 2019 at 11:59 PM H.J. Lu <hjl.tools@gmail.com> wrote: > > > > Since MMX intrinsics are marked with SSE/SSE2/SSSE3 for SSE emulation, > > enable them without SSE/SSE2/SSSE3 if MMX is enabled. > > > > Restore TARGET_3DNOW check, which was changed to TARGET_3DNOW_A by > > revision 271235. > > > > gcc/ > > > > PR target/90497 > > * config/i386/i386-expand.c (ix86_expand_builtin): Enable MMX > > intrinsics without SSE/SSE2/SSSE3. > > * config/i386/mmx.md (mmx_uavgv8qi3): Restore TARGET_3DNOW > > check. > > (*mmx_uavgv8qi3): Likewise. > > OK with a small nit. > > Thanks, > Uros. > > > > > gcc/testsuite/ > > > > PR target/90497 > > * gcc.target/i386/pr90497-1.c: New test. > > * gcc.target/i386/pr90497-2.c: Likewise. > > --- > > gcc/config/i386/i386-expand.c | 6 ++++-- > > gcc/config/i386/mmx.md | 4 ++-- > > gcc/testsuite/gcc.target/i386/pr90497-1.c | 12 ++++++++++++ > > gcc/testsuite/gcc.target/i386/pr90497-2.c | 11 +++++++++++ > > 4 files changed, 29 insertions(+), 4 deletions(-) > > create mode 100644 gcc/testsuite/gcc.target/i386/pr90497-1.c > > create mode 100644 gcc/testsuite/gcc.target/i386/pr90497-2.c > > > > diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c > > index df035607fa7..35aadefdef3 100644 > > --- a/gcc/config/i386/i386-expand.c > > +++ b/gcc/config/i386/i386-expand.c > > @@ -10937,8 +10937,10 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget, > > && (isa & (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4)) != 0) > > isa |= (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4); > > /* Use SSE/SSE2/SSSE3 to emulate MMX intrinsics in 64-bit mode when > > - MMX is disabled. */ > > - if (TARGET_MMX_WITH_SSE) > > + MMX is disabled. NB: Since MMX intrinsics are marked with > > + SSE/SSE2/SSSE3, enable them without SSE/SSE2/SSSE3 if MMX is > > + enabled. */ > > + if (TARGET_MMX_WITH_SSE || TARGET_MMX) > > Please use "TARGET_MMX || TARGET_MMX_WITH_SSE" as is the case with > all these conditions. > This is what I am checking in. Thanks.
diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c index df035607fa7..35aadefdef3 100644 --- a/gcc/config/i386/i386-expand.c +++ b/gcc/config/i386/i386-expand.c @@ -10937,8 +10937,10 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget, && (isa & (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4)) != 0) isa |= (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4); /* Use SSE/SSE2/SSSE3 to emulate MMX intrinsics in 64-bit mode when - MMX is disabled. */ - if (TARGET_MMX_WITH_SSE) + MMX is disabled. NB: Since MMX intrinsics are marked with + SSE/SSE2/SSSE3, enable them without SSE/SSE2/SSSE3 if MMX is + enabled. */ + if (TARGET_MMX_WITH_SSE || TARGET_MMX) { if (((bisa & (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX)) == (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX)) diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 29bcf931836..adad950fa04 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -1745,7 +1745,7 @@ (const_int 1) (const_int 1)])) (const_int 1))))] "(TARGET_MMX || TARGET_MMX_WITH_SSE) - && (TARGET_SSE || TARGET_3DNOW_A)" + && (TARGET_SSE || TARGET_3DNOW)" "ix86_fixup_binary_operands_no_copy (PLUS, V8QImode, operands);") (define_insn "*mmx_uavgv8qi3" @@ -1764,7 +1764,7 @@ (const_int 1) (const_int 1)])) (const_int 1))))] "(TARGET_MMX || TARGET_MMX_WITH_SSE) - && (TARGET_SSE || TARGET_3DNOW_A) + && (TARGET_SSE || TARGET_3DNOW) && ix86_binary_operator_ok (PLUS, V8QImode, operands)" { /* These two instructions have the same operation, but their encoding diff --git a/gcc/testsuite/gcc.target/i386/pr90497-1.c b/gcc/testsuite/gcc.target/i386/pr90497-1.c new file mode 100644 index 00000000000..ed6ded7efbc --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr90497-1.c @@ -0,0 +1,12 @@ +/* PR target/90497 */ +/* { dg-do compile } */ +/* { dg-options "-mno-sse -mmmx" { target ia32 } } */ +/* { dg-options "-mno-mmx" { target { ! ia32 } } } */ + +typedef char __v8qi __attribute__ ((__vector_size__ (8))); + +__v8qi +foo (__v8qi x, __v8qi y) +{ + return __builtin_ia32_pcmpeqb (x, y); +} diff --git a/gcc/testsuite/gcc.target/i386/pr90497-2.c b/gcc/testsuite/gcc.target/i386/pr90497-2.c new file mode 100644 index 00000000000..99ee5756b76 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr90497-2.c @@ -0,0 +1,11 @@ +/* PR target/90497 */ +/* { dg-do compile { target ia32 } } */ +/* { dg-options "-mno-sse -m3dnow" } */ + +typedef char __v8qi __attribute__ ((__vector_size__ (8))); + +__v8qi +foo (__v8qi x, __v8qi y) +{ + return __builtin_ia32_pavgusb (x, y); +}