[U-Boot,12/15] i.MX7ULP: Workaround APLL PFD2 to 345.6Mhz
diff mbox series

Message ID 20190516033236.10594-12-peng.fan@nxp.com
State New
Delegated to: Stefano Babic
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Series
  • [U-Boot,01/15] mx7ulp: Add common plugin codes for mx7ulp
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Commit Message

Peng Fan May 16, 2019, 3:19 a.m. UTC
From: Ye Li <ye.li@nxp.com>

The GPU uses APLL PFD2 as its clock parent (483.84Mhz) with divider
set to 1. This frequecy is out of ULP A0 spec. The MAX rate for GPU
is 350Mhz. So we simply configure the APLL PFD2 to 345.6Mhz (FRAC=28)
to workaround the problem. The correct fix should let GPU handle the
clock rate in kernel.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/mach-imx/mx7ulp/clock.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Patch
diff mbox series

diff --git a/arch/arm/mach-imx/mx7ulp/clock.c b/arch/arm/mach-imx/mx7ulp/clock.c
index 0a0165cad2..6d6697ad99 100644
--- a/arch/arm/mach-imx/mx7ulp/clock.c
+++ b/arch/arm/mach-imx/mx7ulp/clock.c
@@ -300,9 +300,9 @@  void clock_init(void)
 
 	scg_a7_soscdiv_init();
 
-	/* APLL PFD1 = 270Mhz, PFD2=480Mhz, PFD3=800Mhz */
+	/* APLL PFD1 = 270Mhz, PFD2=345.6Mhz, PFD3=800Mhz */
 	scg_enable_pll_pfd(SCG_APLL_PFD1_CLK, 35);
-	scg_enable_pll_pfd(SCG_APLL_PFD2_CLK, 20);
+	scg_enable_pll_pfd(SCG_APLL_PFD2_CLK, 28);
 	scg_enable_pll_pfd(SCG_APLL_PFD3_CLK, 12);
 
 	init_clk_lpuart();