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Thu, 16 May 2019 03:19:04 +0000 Received: from AM0PR04MB4481.eurprd04.prod.outlook.com ([fe80::3173:24:d401:2378]) by AM0PR04MB4481.eurprd04.prod.outlook.com ([fe80::3173:24:d401:2378%6]) with mapi id 15.20.1878.024; Thu, 16 May 2019 03:19:04 +0000 From: Peng Fan To: "sbabic@denx.de" , "festevam@gmail.com" Thread-Topic: [PATCH 06/15] i.MX7ULP: Fix PCC register bits mask and offset issue Thread-Index: AQHVC5YdXaSawipk90+awcPWgMepAQ== Date: Thu, 16 May 2019 03:19:04 +0000 Message-ID: <20190516033236.10594-6-peng.fan@nxp.com> References: <20190516033236.10594-1-peng.fan@nxp.com> In-Reply-To: <20190516033236.10594-1-peng.fan@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.16.4 x-clientproxiedby: HK2PR0401CA0008.apcprd04.prod.outlook.com (2603:1096:202:2::18) To AM0PR04MB4481.eurprd04.prod.outlook.com (2603:10a6:208:70::15) authentication-results: spf=none (sender IP is ) smtp.mailfrom=peng.fan@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [119.31.174.71] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: dc9b2510-8e59-4b4e-bbe9-08d6d9ad3f88 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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H:AM0PR04MB4481.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: RzOKRaUpPOYru/hGtfS57/czmg7af5yp9G+ESaLJ3DfnIFHYNdGNhB6X/50byb9oucW76KQJGcH64eDLyTryZ7ENfwoAIHFZWJryT1wozebmGDXeMfaweWmIzyIxq4rhKm1QU5Cc4Pje44xoQie1DYIVL3oFKLrfwlLTcF2xw5k0wR0Mnlz2Rg0UODbUlfUEYnWkyuFD9Pug3sp5y+f8dVGnJKr19JMoUro4LHsUZViwdh6RI5XTDcJ5wXDKlC1L0QY3OjDzmTI16LF5aODB9XcsR6psPhjdLvb5pJAZjpHXenqBUCQ+gLC9kkxrCmlBi/ALn797zX1xzmKB/NzDnIAGXTPL87bPGI0qKekXay504UTpPrkmScvGLxM7oQZlJunKWArKUoOw6/ENfoyE07x05js3sk7pC8jZMDbb4M0= MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: dc9b2510-8e59-4b4e-bbe9-08d6d9ad3f88 X-MS-Exchange-CrossTenant-originalarrivaltime: 16 May 2019 03:19:04.2466 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR04MB6594 Cc: "u-boot@lists.denx.de" , dl-uboot-imx Subject: [U-Boot] [PATCH 06/15] i.MX7ULP: Fix PCC register bits mask and offset issue X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Ye Li The offset for FRAC and the mask for PCD are not correct. If we set FRAC, we can't get the right frequency. Fix them to correct value. Signed-off-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/include/asm/arch-mx7ulp/pcc.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-mx7ulp/pcc.h b/arch/arm/include/asm/arch-mx7ulp/pcc.h index 67a0936150..dee3cfcdc0 100644 --- a/arch/arm/include/asm/arch-mx7ulp/pcc.h +++ b/arch/arm/include/asm/arch-mx7ulp/pcc.h @@ -289,10 +289,10 @@ enum pcc3_entry { #define PCC_INUSE_MASK (0x1 << PCC_INUSE_OFFSET) #define PCC_PCS_OFFSET 24 #define PCC_PCS_MASK (0x7 << PCC_PCS_OFFSET) -#define PCC_FRAC_OFFSET 4 +#define PCC_FRAC_OFFSET 3 #define PCC_FRAC_MASK (0x1 << PCC_FRAC_OFFSET) #define PCC_PCD_OFFSET 0 -#define PCC_PCD_MASK (0xf << PCC_PCD_OFFSET) +#define PCC_PCD_MASK (0x7 << PCC_PCD_OFFSET) enum pcc_clksrc_type {