[U-Boot,4/5] mx7ulp: Select the SCG1 APLL PFD as a systemclock source
diff mbox series

Message ID 20190515101032.11905-5-peng.fan@nxp.com
State New
Delegated to: Stefano Babic
Headers show
Series
  • i.MX7ULP EVK: update ddr script to make boardboot
Related show

Commit Message

Peng Fan May 15, 2019, 9:56 a.m. UTC
From: Ye Li <ye.li@nxp.com>

Due to the APLL out glitch issue, the APLLCFG PLLS bit must
be set to select SCG1 APLL PFD for generating system clock to align
with the design.

Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
---
 board/freescale/mx7ulp_evk/imximage.cfg | 2 +-
 board/freescale/mx7ulp_evk/plugin.S     | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

Patch
diff mbox series

diff --git a/board/freescale/mx7ulp_evk/imximage.cfg b/board/freescale/mx7ulp_evk/imximage.cfg
index d4f6c3c62d..6bc7c199f5 100644
--- a/board/freescale/mx7ulp_evk/imximage.cfg
+++ b/board/freescale/mx7ulp_evk/imximage.cfg
@@ -45,7 +45,7 @@  DATA 4   0x403f00dc 0x00000000
 DATA 4   0x403e0040 0x01000020
 DATA 4   0x403e0500 0x01000000
 DATA 4   0x403e050c 0x80808080
-DATA 4   0x403e0508 0x00160000
+DATA 4   0x403e0508 0x00160002
 DATA 4   0x403E0510 0x00000002
 DATA 4   0x403E0514 0x00000005
 DATA 4   0x403e0500 0x00000001
diff --git a/board/freescale/mx7ulp_evk/plugin.S b/board/freescale/mx7ulp_evk/plugin.S
index ccd2fc03a4..55dfecc751 100644
--- a/board/freescale/mx7ulp_evk/plugin.S
+++ b/board/freescale/mx7ulp_evk/plugin.S
@@ -18,7 +18,7 @@ 
 
 	ldr r3, =0x80808080
 	str r3, [r2, #0x50c]
-	ldr r3, =0x00160000
+	ldr r3, =0x00160002
 	str r3, [r2, #0x508]
 	ldr r3, =0x00000002
 	str r3, [r2, #0x510]