[U-Boot,1/5] mx7ulp: Fix APLL num and denom setting issue
diff mbox series

Message ID 20190515101032.11905-2-peng.fan@nxp.com
State New
Delegated to: Stefano Babic
Headers show
  • i.MX7ULP EVK: update ddr script to make boardboot
Related show

Commit Message

Peng Fan May 15, 2019, 9:56 a.m. UTC
From: Ye Li <ye.li@nxp.com>

For the current APLL setting, as we want the APLL PFD0 to meet DDR clock 320Mhz requirement.
We set MULT to 20, NUM to 4 and DENOM to 2, to get final 22 multiplier. But according to the RM,
the NUM should always be less than the DENOM. So our setting violates the rule.

Actually the ROM has already set the MULT to 22 and leave NUM/DENOM in default value. The calculated APLL PFD0 clock
is 318.9888Mhz, which also meet the DDR requirement.
To fix the issue, we remove the PLL settings in DCD to use default value from ROM, and only set the PFD0 FRAC.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
 board/freescale/mx7ulp_evk/imximage.cfg |  6 ------
 board/freescale/mx7ulp_evk/plugin.S     | 19 +------------------
 2 files changed, 1 insertion(+), 24 deletions(-)

diff mbox series

diff --git a/board/freescale/mx7ulp_evk/imximage.cfg b/board/freescale/mx7ulp_evk/imximage.cfg
index a6e18d9440..78df69f40e 100644
--- a/board/freescale/mx7ulp_evk/imximage.cfg
+++ b/board/freescale/mx7ulp_evk/imximage.cfg
@@ -43,13 +43,7 @@  CSF CONFIG_CSF_SIZE
 DATA 4   0x403f00dc 0x00000000
 DATA 4   0x403e0040 0x01000020
-DATA 4   0x403e0500 0x01000000
 DATA 4   0x403e050c 0x80808080
-DATA 4   0x403e0508 0x00140000
-DATA 4   0x403E0510 0x00000004
-DATA 4   0x403E0514 0x00000002
-DATA 4   0x403e0500 0x00000001
-CHECK_BITS_SET 4 0x403e0500 0x01000000
 DATA 4   0x403e050c 0x8080801E
 CHECK_BITS_SET 4 0x403e050c 0x00000040
 DATA 4   0x403E0030 0x00000001
diff --git a/board/freescale/mx7ulp_evk/plugin.S b/board/freescale/mx7ulp_evk/plugin.S
index 082b2beaa3..802ae5f49a 100644
--- a/board/freescale/mx7ulp_evk/plugin.S
+++ b/board/freescale/mx7ulp_evk/plugin.S
@@ -13,26 +13,9 @@ 
 	ldr r2, =0x403e0000
 	ldr r3, =0x01000020
 	str r3, [r2, #0x40]
-	ldr r3, =0x01000000
-	str r3, [r2, #0x500]
 	ldr r3, =0x80808080
 	str r3, [r2, #0x50c]
-	ldr r3, =0x00140000
-	str r3, [r2, #0x508]
-	ldr r3, =0x00000004
-	str r3, [r2, #0x510]
-	ldr r3, =0x00000002
-	str r3, [r2, #0x514]
-	ldr r3, =0x00000001
-	str r3, [r2, #0x500]
-	ldr r3, =0x01000000
-	ldr r4, [r2, #0x500]
-	and r4, r3
-	cmp r4, r3
-	bne wait1
 	ldr r3, =0x8080801E
 	str r3, [r2, #0x50c]