Message ID | 20190515072747.39941-1-xiaowei.bao@nxp.com |
---|---|
State | Not Applicable, archived |
Headers | show |
Series | [1/3] dt-bindings: pci: layerscape-pci: add compatible strings"fsl, ls1028a-pcie" | expand |
Context | Check | Description |
---|---|---|
robh/checkpatch | success |
Hi Arndt, -----Original Message----- From: Arnd Bergmann <arnd@arndb.de> Sent: 2019年5月17日 16:59 To: Xiaowei Bao <xiaowei.bao@nxp.com> Cc: Bjorn Helgaas <bhelgaas@google.com>; Rob Herring <robh+dt@kernel.org>; Mark Rutland <mark.rutland@arm.com>; Shawn Guo <shawnguo@kernel.org>; Leo Li <leoyang.li@nxp.com>; Kishon <kishon@ti.com>; Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>; gregkh <gregkh@linuxfoundation.org>; M.h. Lian <minghuan.lian@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; Roy Zang <roy.zang@nxp.com>; Kate Stewart <kstewart@linuxfoundation.org>; Philippe Ombredanne <pombredanne@nexb.com>; Shawn Lin <shawn.lin@rock-chips.com>; linux-pci <linux-pci@vger.kernel.org>; DTML <devicetree@vger.kernel.org>; Linux Kernel Mailing List <linux-kernel@vger.kernel.org>; Linux ARM <linux-arm-kernel@lists.infradead.org>; linuxppc-dev <linuxppc-dev@lists.ozlabs.org> Subject: Re: [EXT] Re: [PATCH 2/3] arm64: dts: ls1028a: Add PCIe controller DT nodes Caution: EXT Email On Fri, May 17, 2019 at 5:21 AM Xiaowei Bao <xiaowei.bao@nxp.com> wrote: > -----Original Message----- > From: Arnd Bergmann <arnd@arndb.de> > On Wed, May 15, 2019 at 9:36 AM Xiaowei Bao <xiaowei.bao@nxp.com> wrote: > > Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> > > --- > > arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 52 ++++++++++++++++++++++++ > > 1 files changed, 52 insertions(+), 0 deletions(-) > > > > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi > > b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi > > index b045812..50b579b 100644 > > --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi > > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi > > @@ -398,6 +398,58 @@ > > status = "disabled"; > > }; > > > > + pcie@3400000 { > > + compatible = "fsl,ls1028a-pcie"; > > + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ > > + 0x80 0x00000000 0x0 0x00002000>; /* configuration space */ > > + reg-names = "regs", "config"; > > + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ > > + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ > > + interrupt-names = "pme", "aer"; > > + #address-cells = <3>; > > + #size-cells = <2>; > > + device_type = "pci"; > > + dma-coherent; > > + num-lanes = <4>; > > + bus-range = <0x0 0xff>; > > + ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000 /* downstream I/O */ > > + 0x82000000 0x0 0x40000000 0x80 > > + 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ > > Are you sure there is no support for 64-bit BARs or prefetchable memory? > [Xiaowei Bao] sorry for late reply, Thought that our Layerscape platform has not added prefetchable memory support in DTS, so this platform has not been added, I will submit a separate patch to add prefetchable memory support for all Layerscape platforms. Ok, thanks. > Of course, the prefetchable PCIE device can work in our boards, > because the RC will assign non-prefetchable memory for this device. We > reserve 1G no-prefetchable memory for PCIE device, it is enough for general devices. Sure, many devices work just fine, this is mostly a question of supporting those devices that do require multiple gigabytes, or that need prefetchable memory semantics to get the expected performance. GPUs are the obvious example, but I think there are others (infiniband?). [Xiaowei Bao] sorry, I don't know much about infiniband and GPU, as you said, I think many devices works fine with this DTS, I will add the prefetchable memory entry in DTS future and submit another patch. Arnd
On Wed, 15 May 2019 15:27:45 +0800, Xiaowei Bao wrote: > Add the PCIe compatible string for LS1028A > > Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> > --- > .../devicetree/bindings/pci/layerscape-pci.txt | 1 + > 1 files changed, 1 insertions(+), 0 deletions(-) > Reviewed-by: Rob Herring <robh@kernel.org>
> -----Original Message----- > From: Rob Herring <robh@kernel.org> > Sent: 2019年6月14日 5:00 > To: Xiaowei Bao <xiaowei.bao@nxp.com> > Cc: bhelgaas@google.com; robh+dt@kernel.org; mark.rutland@arm.com; > shawnguo@kernel.org; Leo Li <leoyang.li@nxp.com>; kishon@ti.com; > lorenzo.pieralisi@arm.com; arnd@arndb.de; gregkh@linuxfoundation.org; > M.h. Lian <minghuan.lian@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; > Roy Zang <roy.zang@nxp.com>; kstewart@linuxfoundation.org; > pombredanne@nexb.com; shawn.lin@rock-chips.com; > linux-pci@vger.kernel.org; devicetree@vger.kernel.org; > linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; > linuxppc-dev@lists.ozlabs.org; Xiaowei Bao <xiaowei.bao@nxp.com> > Subject: [EXT] Re: [PATCH 1/3] dt-bindings: pci: layerscape-pci: add > compatible strings "fsl,ls1028a-pcie" > > Caution: EXT Email > > On Wed, 15 May 2019 15:27:45 +0800, Xiaowei Bao wrote: > > Add the PCIe compatible string for LS1028A > > > > Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> > > --- > > .../devicetree/bindings/pci/layerscape-pci.txt | 1 + > > 1 files changed, 1 insertions(+), 0 deletions(-) > > > > Reviewed-by: Rob Herring <robh@kernel.org> [Xiaowei Bao] thanks a lot for your review.
diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index e20ceaa..99a386e 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -21,6 +21,7 @@ Required properties: "fsl,ls1046a-pcie" "fsl,ls1043a-pcie" "fsl,ls1012a-pcie" + "fsl,ls1028a-pcie" EP mode: "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep" - reg: base addresses and lengths of the PCIe controller register blocks.
Add the PCIe compatible string for LS1028A Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> --- .../devicetree/bindings/pci/layerscape-pci.txt | 1 + 1 files changed, 1 insertions(+), 0 deletions(-)