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[i386] : Macroize ashrsi3_cvt and ashrdi3_cvt patterns

Message ID CAFULd4avU7gExun5+=3j6-mN0RsANFEL566_2M-3DCkdFBtaLA@mail.gmail.com
State New
Headers show
Series [i386] : Macroize ashrsi3_cvt and ashrdi3_cvt patterns | expand

Commit Message

Uros Bizjak May 7, 2019, 9:38 p.m. UTC 
2019-05-07  Uroš Bizjak  <ubizjak@gmail.com>

    * config/i386/i386.md (cvt_mnemonic): New mode attribute.
    (ashr<mode>3_cvt): Merge insn pattern from ashrsi3_cvt and
    ashrdi3_cvt using SWI48 mode iterator.

Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.
Committed to mainline SVN.

Uros.
diff mbox series

Patch

Index: config/i386/i386.md
===================================================================
--- config/i386/i386.md	(revision 270954)
+++ config/i386/i386.md	(working copy)
@@ -10872,22 +10872,27 @@ 
    (set_attr "amdfam10_decode" "vector")
    (set_attr "bdver1_decode" "vector")])
 
-(define_insn "ashrdi3_cvt"
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=*d,rm")
-	(ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "*a,0")
-		     (match_operand:QI 2 "const_int_operand")))
+;; Base name for insn mnemonic.
+(define_mode_attr cvt_mnemonic
+  [(SI "{cltd|cdq}") (DI "{cqto|cqo}")])
+
+(define_insn "ashr<mode>3_cvt"
+  [(set (match_operand:SWI48 0 "nonimmediate_operand" "=*d,rm")
+	(ashiftrt:SWI48
+	  (match_operand:SWI48 1 "nonimmediate_operand" "*a,0")
+	  (match_operand:QI 2 "const_int_operand")))
    (clobber (reg:CC FLAGS_REG))]
-  "TARGET_64BIT && INTVAL (operands[2]) == 63
+  "INTVAL (operands[2]) == GET_MODE_BITSIZE (<MODE>mode)-1
    && (TARGET_USE_CLTD || optimize_function_for_size_p (cfun))
-   && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
+   && ix86_binary_operator_ok (ASHIFTRT, <MODE>mode, operands)"
   "@
-   {cqto|cqo}
-   sar{q}\t{%2, %0|%0, %2}"
+   <cvt_mnemonic>
+   sar{<imodesuffix>}\t{%2, %0|%0, %2}"
   [(set_attr "type" "imovx,ishift")
    (set_attr "prefix_0f" "0,*")
    (set_attr "length_immediate" "0,*")
    (set_attr "modrm" "0,1")
-   (set_attr "mode" "DI")])
+   (set_attr "mode" "<MODE>")])
 
 (define_insn "*ashrsi3_cvt_zext"
   [(set (match_operand:DI 0 "register_operand" "=*d,r")
@@ -10907,23 +10912,6 @@ 
    (set_attr "modrm" "0,1")
    (set_attr "mode" "SI")])
 
-(define_insn "ashrsi3_cvt"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,rm")
-	(ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "*a,0")
-		     (match_operand:QI 2 "const_int_operand")))
-   (clobber (reg:CC FLAGS_REG))]
-  "INTVAL (operands[2]) == 31
-   && (TARGET_USE_CLTD || optimize_function_for_size_p (cfun))
-   && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
-  "@
-   {cltd|cdq}
-   sar{l}\t{%2, %0|%0, %2}"
-  [(set_attr "type" "imovx,ishift")
-   (set_attr "prefix_0f" "0,*")
-   (set_attr "length_immediate" "0,*")
-   (set_attr "modrm" "0,1")
-   (set_attr "mode" "SI")])
-
 (define_expand "x86_shift<mode>_adj_3"
   [(use (match_operand:SWI48 0 "register_operand"))
    (use (match_operand:SWI48 1 "register_operand"))