| Message ID | 20190507192055.13093-1-marex@denx.de |
|---|---|
| State | Accepted, archived |
| Delegated to: | Simon Goldschmidt |
| Headers | show |
| Series | [U-Boot,1/2] ARM: socfpga: Pull PL310 clearing into common code | expand |
On 07.05.19 21:20, Marek Vasut wrote: > Pull the PL310 clearing code into common code, so it can be reused > by Arria10. > > Signed-off-by: Marek Vasut <marex@denx.de> > Cc: Chin Liang See <chin.liang.see@intel.com> > Cc: Dalon Westergreen <dwesterg@gmail.com> > Cc: Dinh Nguyen <dinguyen@kernel.org> > Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> > Cc: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> > --- > arch/arm/mach-socfpga/include/mach/misc.h | 1 + > arch/arm/mach-socfpga/misc.c | 54 +++++++++++++++++++++++ > arch/arm/mach-socfpga/spl_gen5.c | 54 ----------------------- > 3 files changed, 55 insertions(+), 54 deletions(-) > > diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h > index c3ca8cdf3b..27d0b6a370 100644 > --- a/arch/arm/mach-socfpga/include/mach/misc.h > +++ b/arch/arm/mach-socfpga/include/mach/misc.h > @@ -40,5 +40,6 @@ void socfpga_sdram_remap_zero(void); > #endif > > void do_bridge_reset(int enable, unsigned int mask); > +void socfpga_pl310_clear(void); > > #endif /* _MISC_H_ */ > diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c > index d887f0201f..410d5a8b49 100644 > --- a/arch/arm/mach-socfpga/misc.c > +++ b/arch/arm/mach-socfpga/misc.c > @@ -46,6 +46,60 @@ int dram_init(void) > return 0; > } > > +void socfpga_pl310_clear(void) > +{ > + u32 mask = 0xff, ena = 0; > + > + icache_enable(); > + > + /* Disable the L2 cache */ > + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); > + > + writel(0x0, &pl310->pl310_tag_latency_ctrl); > + writel(0x10, &pl310->pl310_data_latency_ctrl); > + > + /* enable BRESP, instruction and data prefetch, full line of zeroes */ > + setbits_le32(&pl310->pl310_aux_ctrl, > + L310_AUX_CTRL_DATA_PREFETCH_MASK | > + L310_AUX_CTRL_INST_PREFETCH_MASK | > + L310_SHARED_ATT_OVERRIDE_ENABLE); > + > + /* Enable the L2 cache */ > + ena = readl(&pl310->pl310_ctrl); > + ena |= L2X0_CTRL_EN; > + > + /* > + * Invalidate the PL310 L2 cache. Keep the invalidation code > + * entirely in L1 I-cache to avoid any bus traffic through > + * the L2. > + */ > + asm volatile( > + ".align 5 \n" > + " b 3f \n" > + "1: str %1, [%4] \n" > + " dsb \n" > + " isb \n" > + " str %0, [%2] \n" > + " dsb \n" > + " isb \n" > + "2: ldr %0, [%2] \n" > + " cmp %0, #0 \n" > + " bne 2b \n" > + " str %0, [%3] \n" > + " dsb \n" > + " isb \n" > + " b 4f \n" > + "3: b 1b \n" > + "4: nop \n" > + : "+r"(mask), "+r"(ena) > + : "r"(&pl310->pl310_inv_way), > + "r"(&pl310->pl310_cache_sync), "r"(&pl310->pl310_ctrl) > + : "memory", "cc"); > + > + /* Disable the L2 cache */ > + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); > +} > + > void enable_caches(void) > { > #ifndef CONFIG_SYS_ICACHE_OFF > diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c > index bd2a9fe5ae..65ecba1a31 100644 > --- a/arch/arm/mach-socfpga/spl_gen5.c > +++ b/arch/arm/mach-socfpga/spl_gen5.c > @@ -63,60 +63,6 @@ u32 spl_boot_mode(const u32 boot_device) > } > #endif > > -static void socfpga_pl310_clear(void) > -{ > - u32 mask = 0xff, ena = 0; > - > - icache_enable(); > - > - /* Disable the L2 cache */ > - clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); > - > - writel(0x111, &pl310->pl310_tag_latency_ctrl); > - writel(0x121, &pl310->pl310_data_latency_ctrl); > - > - /* enable BRESP, instruction and data prefetch, full line of zeroes */ > - setbits_le32(&pl310->pl310_aux_ctrl, > - L310_AUX_CTRL_DATA_PREFETCH_MASK | > - L310_AUX_CTRL_INST_PREFETCH_MASK | > - L310_SHARED_ATT_OVERRIDE_ENABLE); > - > - /* Enable the L2 cache */ > - ena = readl(&pl310->pl310_ctrl); > - ena |= L2X0_CTRL_EN; > - > - /* > - * Invalidate the PL310 L2 cache. Keep the invalidation code > - * entirely in L1 I-cache to avoid any bus traffic through > - * the L2. > - */ > - asm volatile( > - ".align 5 \n" > - " b 3f \n" > - "1: str %1, [%4] \n" > - " dsb \n" > - " isb \n" > - " str %0, [%2] \n" > - " dsb \n" > - " isb \n" > - "2: ldr %0, [%2] \n" > - " cmp %0, #0 \n" > - " bne 2b \n" > - " str %0, [%3] \n" > - " dsb \n" > - " isb \n" > - " b 4f \n" > - "3: b 1b \n" > - "4: nop \n" > - : "+r"(mask), "+r"(ena) > - : "r"(&pl310->pl310_inv_way), > - "r"(&pl310->pl310_cache_sync), "r"(&pl310->pl310_ctrl) > - : "memory", "cc"); > - > - /* Disable the L2 cache */ > - clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); > -} > - > void board_init_f(ulong dummy) > { > const struct cm_config *cm_default_cfg = cm_get_default_config(); >
diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h index c3ca8cdf3b..27d0b6a370 100644 --- a/arch/arm/mach-socfpga/include/mach/misc.h +++ b/arch/arm/mach-socfpga/include/mach/misc.h @@ -40,5 +40,6 @@ void socfpga_sdram_remap_zero(void); #endif void do_bridge_reset(int enable, unsigned int mask); +void socfpga_pl310_clear(void); #endif /* _MISC_H_ */ diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index d887f0201f..410d5a8b49 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -46,6 +46,60 @@ int dram_init(void) return 0; } +void socfpga_pl310_clear(void) +{ + u32 mask = 0xff, ena = 0; + + icache_enable(); + + /* Disable the L2 cache */ + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); + + writel(0x0, &pl310->pl310_tag_latency_ctrl); + writel(0x10, &pl310->pl310_data_latency_ctrl); + + /* enable BRESP, instruction and data prefetch, full line of zeroes */ + setbits_le32(&pl310->pl310_aux_ctrl, + L310_AUX_CTRL_DATA_PREFETCH_MASK | + L310_AUX_CTRL_INST_PREFETCH_MASK | + L310_SHARED_ATT_OVERRIDE_ENABLE); + + /* Enable the L2 cache */ + ena = readl(&pl310->pl310_ctrl); + ena |= L2X0_CTRL_EN; + + /* + * Invalidate the PL310 L2 cache. Keep the invalidation code + * entirely in L1 I-cache to avoid any bus traffic through + * the L2. + */ + asm volatile( + ".align 5 \n" + " b 3f \n" + "1: str %1, [%4] \n" + " dsb \n" + " isb \n" + " str %0, [%2] \n" + " dsb \n" + " isb \n" + "2: ldr %0, [%2] \n" + " cmp %0, #0 \n" + " bne 2b \n" + " str %0, [%3] \n" + " dsb \n" + " isb \n" + " b 4f \n" + "3: b 1b \n" + "4: nop \n" + : "+r"(mask), "+r"(ena) + : "r"(&pl310->pl310_inv_way), + "r"(&pl310->pl310_cache_sync), "r"(&pl310->pl310_ctrl) + : "memory", "cc"); + + /* Disable the L2 cache */ + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); +} + void enable_caches(void) { #ifndef CONFIG_SYS_ICACHE_OFF diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c index bd2a9fe5ae..65ecba1a31 100644 --- a/arch/arm/mach-socfpga/spl_gen5.c +++ b/arch/arm/mach-socfpga/spl_gen5.c @@ -63,60 +63,6 @@ u32 spl_boot_mode(const u32 boot_device) } #endif -static void socfpga_pl310_clear(void) -{ - u32 mask = 0xff, ena = 0; - - icache_enable(); - - /* Disable the L2 cache */ - clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); - - writel(0x111, &pl310->pl310_tag_latency_ctrl); - writel(0x121, &pl310->pl310_data_latency_ctrl); - - /* enable BRESP, instruction and data prefetch, full line of zeroes */ - setbits_le32(&pl310->pl310_aux_ctrl, - L310_AUX_CTRL_DATA_PREFETCH_MASK | - L310_AUX_CTRL_INST_PREFETCH_MASK | - L310_SHARED_ATT_OVERRIDE_ENABLE); - - /* Enable the L2 cache */ - ena = readl(&pl310->pl310_ctrl); - ena |= L2X0_CTRL_EN; - - /* - * Invalidate the PL310 L2 cache. Keep the invalidation code - * entirely in L1 I-cache to avoid any bus traffic through - * the L2. - */ - asm volatile( - ".align 5 \n" - " b 3f \n" - "1: str %1, [%4] \n" - " dsb \n" - " isb \n" - " str %0, [%2] \n" - " dsb \n" - " isb \n" - "2: ldr %0, [%2] \n" - " cmp %0, #0 \n" - " bne 2b \n" - " str %0, [%3] \n" - " dsb \n" - " isb \n" - " b 4f \n" - "3: b 1b \n" - "4: nop \n" - : "+r"(mask), "+r"(ena) - : "r"(&pl310->pl310_inv_way), - "r"(&pl310->pl310_cache_sync), "r"(&pl310->pl310_ctrl) - : "memory", "cc"); - - /* Disable the L2 cache */ - clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); -} - void board_init_f(ulong dummy) { const struct cm_config *cm_default_cfg = cm_get_default_config();
Pull the PL310 clearing code into common code, so it can be reused by Arria10. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dalon Westergreen <dwesterg@gmail.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com> --- arch/arm/mach-socfpga/include/mach/misc.h | 1 + arch/arm/mach-socfpga/misc.c | 54 +++++++++++++++++++++++ arch/arm/mach-socfpga/spl_gen5.c | 54 ----------------------- 3 files changed, 55 insertions(+), 54 deletions(-)