From patchwork Thu Aug 11 14:35:44 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aneesh V X-Patchwork-Id: 109616 X-Patchwork-Delegate: albert.aribaud@free.fr Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 98780B6F8E for ; Fri, 12 Aug 2011 00:40:54 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A9EB5281BC; Thu, 11 Aug 2011 16:40:52 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id fk960WIakeW3; Thu, 11 Aug 2011 16:40:52 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id EEFC0281B9; Thu, 11 Aug 2011 16:40:49 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1E10E281BE for ; Thu, 11 Aug 2011 16:40:48 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id wMlveuLQrLBQ for ; Thu, 11 Aug 2011 16:40:47 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from bear.ext.ti.com (bear.ext.ti.com [192.94.94.41]) by theia.denx.de (Postfix) with ESMTPS id B79DD2819B for ; Thu, 11 Aug 2011 16:40:45 +0200 (CEST) Received: from dbdp20.itg.ti.com ([172.24.170.38]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id p7BEeXTI026888 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 11 Aug 2011 09:40:35 -0500 Received: from dbde70.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id p7BEeVvP027041; Thu, 11 Aug 2011 20:10:32 +0530 (IST) Received: from dbdp31.itg.ti.com (172.24.170.98) by DBDE70.ent.ti.com (172.24.170.148) with Microsoft SMTP Server id 8.3.106.1; Thu, 11 Aug 2011 20:10:31 +0530 Received: from localhost (a0393566pc.apr.dhcp.ti.com [172.24.137.55]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id p7BEeVb4016167; Thu, 11 Aug 2011 20:10:31 +0530 (IST) From: Aneesh V To: Date: Thu, 11 Aug 2011 20:05:44 +0530 Message-ID: <1313073345-29773-4-git-send-email-aneesh@ti.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1312197486-31712-2-git-send-email-aneesh@ti.com> References: <1312197486-31712-2-git-send-email-aneesh@ti.com> MIME-Version: 1.0 Cc: santosh.shilimkar@ti.com Subject: [U-Boot] [PATCH v3 3/4] armv7: stronger barrier for cache-maintenance operations X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de set-way operations need a DSB after them to ensure the operation is complete. DMB may not be enough. Use DSB after all operations instead of DMB. Signed-off-by: Aneesh V --- arch/arm/cpu/armv7/cache_v7.c | 12 ++++++------ 1 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c index 3e1e1bf..665f025 100644 --- a/arch/arm/cpu/armv7/cache_v7.c +++ b/arch/arm/cpu/armv7/cache_v7.c @@ -81,8 +81,8 @@ static void v7_inval_dcache_level_setway(u32 level, u32 num_sets, : : "r" (setway)); } } - /* DMB to make sure the operation is complete */ - CP15DMB; + /* DSB to make sure the operation is complete */ + CP15DSB; } static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets, @@ -108,8 +108,8 @@ static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets, : : "r" (setway)); } } - /* DMB to make sure the operation is complete */ - CP15DMB; + /* DSB to make sure the operation is complete */ + CP15DSB; } static void v7_maint_dcache_level_setway(u32 level, u32 operation) @@ -227,8 +227,8 @@ static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op) break; } - /* DMB to make sure the operation is complete */ - CP15DMB; + /* DSB to make sure the operation is complete */ + CP15DSB; } /* Invalidate TLB */