@@ -75,7 +75,7 @@ static long fixed_sdram(void)
__udelay(50000);
im->ddr.csbnds[0].csbnds = (msize - 1) >> 24;
- im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG;
+ im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS_CONFIG;
/* Currently we use only one CS, so disable the other bank. */
im->ddr.cs_config[1] = 0;
@@ -130,7 +130,7 @@ int fixed_sdram(void)
im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
#else
im->ddr.csbnds[2].csbnds = 0x0000000f;
- im->ddr.cs_config[2] = CONFIG_SYS_DDR_CONFIG;
+ im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS_CONFIG;
/* currently we use only one CS, so disable the other banks */
im->ddr.cs_config[0] = 0;
@@ -59,7 +59,7 @@ int fixed_sdram(void)
/* Only one CS0 for DDR */
im->ddr.csbnds[0].csbnds = 0x0000000f;
- im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG;
+ im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS_CONFIG;
debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds);
debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]);
@@ -249,8 +249,8 @@ int fixed_sdram(void)
im->ddr.csbnds[0].csbnds = 0x00000007;
im->ddr.csbnds[1].csbnds = 0x0008000f;
- im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG;
- im->ddr.cs_config[1] = CONFIG_SYS_DDR_CONFIG;
+ im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS_CONFIG;
+ im->ddr.cs_config[1] = CONFIG_SYS_DDR_CS_CONFIG;
im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
@@ -108,7 +108,7 @@ int fixed_sdram(void)
#warning Currently any ddr size other than 256 is not supported
#endif
im->ddr.csbnds[2].csbnds = 0x0000000f;
- im->ddr.cs_config[2] = CONFIG_SYS_DDR_CONFIG;
+ im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS_CONFIG;
/* currently we use only one CS, so disable the other banks */
im->ddr.cs_config[0] = 0;
@@ -66,7 +66,7 @@ static long fixed_sdram(void)
__udelay(50000);
out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
- out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CONFIG);
+ out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS_CONFIG);
/* Currently we use only one CS, so disable the other bank. */
out_be32(&im->ddr.cs_config[1], 0);
@@ -130,7 +130,7 @@
* seem to have the SPD connected to I2C.
*/
#define CONFIG_SYS_DDR_SIZE 128 /* MB */
-#define CONFIG_SYS_DDR_CONFIG ( CSCONFIG_EN \
+#define CONFIG_SYS_DDR_CS_CONFIG ( CSCONFIG_EN \
| 0x00010000 /* TODO */ \
| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 )
/* 0x80010102 */
@@ -126,7 +126,7 @@
#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
#else
-#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
+#define CONFIG_SYS_DDR_CS_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
#define CONFIG_SYS_DDR_TIMING_1 0x36332321
#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
@@ -202,7 +202,7 @@
#ifndef CONFIG_SPD_EEPROM /* No SPD? Then manually set up DDR parameters */
#define CONFIG_SYS_DDR_SIZE 256 /* Mb */
- #define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
+ #define CONFIG_SYS_DDR_CS_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
#define CONFIG_SYS_DDR_TIMING_1 0x26242321
#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */
@@ -144,7 +144,7 @@
#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
#else
-#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9)
+#define CONFIG_SYS_DDR_CS_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9)
#define CONFIG_SYS_DDR_TIMING_1 0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */
#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* may need tuning */
#define CONFIG_SYS_DDR_CONTROL 0x42008000 /* Self refresh,2T timing */
@@ -114,7 +114,7 @@
* NB: manual DDR setup untested on sbc834x
*/
#define CONFIG_SYS_DDR_SIZE 256 /* MB */
-#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
+#define CONFIG_SYS_DDR_CS_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
#define CONFIG_SYS_DDR_TIMING_1 0x36332321
#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
@@ -79,7 +79,7 @@
* have the SPD connected to I2C.
*/
#define CONFIG_SYS_DDR_SIZE 128 /* MB */
-#define CONFIG_SYS_DDR_CONFIG ( CSCONFIG_EN \
+#define CONFIG_SYS_DDR_CS_CONFIG ( CSCONFIG_EN \
| CSCONFIG_AP \
| 0x00040000 /* TODO */ \
| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 )
The register this is written to is named ddr.cs_config, so name the #define similarly to reduce confusion Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Cc: Kim Phillips <kim.phillips@freescale.com> --- board/freescale/mpc8313erdb/sdram.c | 2 +- board/freescale/mpc8349emds/mpc8349emds.c | 2 +- board/freescale/mpc8349itx/mpc8349itx.c | 2 +- board/freescale/mpc8360emds/mpc8360emds.c | 4 ++-- board/sbc8349/sbc8349.c | 2 +- board/ve8313/ve8313.c | 2 +- include/configs/MPC8313ERDB.h | 2 +- include/configs/MPC8349EMDS.h | 2 +- include/configs/MPC8349ITX.h | 2 +- include/configs/MPC8360EMDS.h | 2 +- include/configs/sbc8349.h | 2 +- include/configs/ve8313.h | 2 +- 12 files changed, 13 insertions(+), 13 deletions(-)