Patchwork [U-Boot,v2,8/8] da850: modifications for Logic PD Rev.3 AM18xx EVM

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Submitter nagabhushana.netagunte@ti.com
Date Aug. 10, 2011, 10:39 a.m.
Message ID <1312972761-24559-9-git-send-email-nagabhushana.netagunte@ti.com>
Download mbox | patch
Permalink /patch/109360/
State Accepted
Commit 0f3d6b06ea06e5b0295e4a8222a25bc95a70c026
Headers show

Comments

nagabhushana.netagunte@ti.com - Aug. 10, 2011, 10:39 a.m.
From: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com>

AHCLKR/UART1_RTS/GP0[11] pin needs to be configured for
NOR to work on Rev.3 EVM. When GP0[11] is low,
the SD0 interface will not work, but NOR flash will.

Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com>
Signed-off-by: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com>
---
 arch/arm/include/asm/arch-davinci/hardware.h |    4 ++++
 board/davinci/da8xxevm/da850evm.c            |   13 +++++++++++++
 2 files changed, 17 insertions(+), 0 deletions(-)

Patch

diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h
index 4a3af7d..692d507 100644
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -159,6 +159,10 @@  typedef volatile unsigned int *	dv_reg_p;
 #define HOST1CFG				(DAVINCI_BOOTCFG_BASE + 0x44)
 #define PSC0_MDCTL				(DAVINCI_PSC0_BASE + 0xa00)
 
+#define GPIO_BANK0_REG_DIR_ADDR			(DAVINCI_GPIO_BASE + 0x10)
+#define GPIO_BANK0_REG_OPDATA_ADDR		(DAVINCI_GPIO_BASE + 0x14)
+#define GPIO_BANK0_REG_SET_ADDR			(DAVINCI_GPIO_BASE + 0x18)
+#define GPIO_BANK0_REG_CLR_ADDR			(DAVINCI_GPIO_BASE + 0x1c)
 #define GPIO_BANK2_REG_DIR_ADDR			(DAVINCI_GPIO_BASE + 0x38)
 #define GPIO_BANK2_REG_OPDATA_ADDR		(DAVINCI_GPIO_BASE + 0x3c)
 #define GPIO_BANK2_REG_SET_ADDR			(DAVINCI_GPIO_BASE + 0x40)
diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c
index 8c3d64e..2f950e7 100644
--- a/board/davinci/da8xxevm/da850evm.c
+++ b/board/davinci/da8xxevm/da850evm.c
@@ -109,6 +109,8 @@  const struct pinmux_config nand_pins[] = {
 #elif defined(CONFIG_USE_NOR)
 /* NOR pin muxer settings */
 const struct pinmux_config nor_pins[] = {
+	/* GP0[11] is required for NOR to work on Rev 3 EVMs */
+	{ pinmux(0), 8, 4 },	/* GP0[11] */
 	{ pinmux(5), 1, 6 },
 	{ pinmux(6), 1, 6 },
 	{ pinmux(7), 1, 0 },
@@ -278,6 +280,7 @@  u32 get_board_rev(void)
 
 int board_init(void)
 {
+	u32 val;
 #ifndef CONFIG_USE_IRQ
 	irq_init();
 #endif
@@ -325,6 +328,16 @@  int board_init(void)
 	if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
 		return 1;
 
+#ifdef CONFIG_USE_NOR
+	/* Set the GPIO direction as output */
+	clrbits_be32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11));
+
+	/* Set the output as low */
+	val = readl(GPIO_BANK0_REG_SET_ADDR);
+	val |= (0x01 << 11);
+	writel(val, GPIO_BANK0_REG_CLR_ADDR);
+#endif
+
 #ifdef CONFIG_DRIVER_TI_EMAC
 	if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0)
 		return 1;