[U-Boot,i.MX8MM+CCF,05/41] clk-provider: sync more clk flags from Linux Kernel
diff mbox series

Message ID 20190430103056.32537-6-peng.fan@nxp.com
State Superseded
Delegated to: Stefano Babic
Headers show
Series
  • i.MX8MM + CCF
Related show

Commit Message

Peng Fan April 30, 2019, 10:17 a.m. UTC
Sync more clk flags that might be used in U-Boot CCF.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 include/linux/clk-provider.h | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

Comments

Lukasz Majewski May 6, 2019, 10:01 p.m. UTC | #1
On Tue, 30 Apr 2019 10:17:47 +0000
Peng Fan <peng.fan@nxp.com> wrote:

> Sync more clk flags that might be used in U-Boot CCF.
> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  include/linux/clk-provider.h | 21 +++++++++++++++++++++
>  1 file changed, 21 insertions(+)
> 
> diff --git a/include/linux/clk-provider.h
> b/include/linux/clk-provider.h index eac045c5f8..3458746a60 100644
> --- a/include/linux/clk-provider.h
> +++ b/include/linux/clk-provider.h
> @@ -9,8 +9,29 @@
>  #ifndef __LINUX_CLK_PROVIDER_H
>  #define __LINUX_CLK_PROVIDER_H
>  
> +/*
> + * flags used across common struct clk.  these flags should only
> affect the
> + * top-level framework.  custom flags for dealing with hardware
> specifics
> + * belong in struct clk_foo
> + *
> + * Please update clk_flags[] in drivers/clk/clk.c when making
> changes here!
> + */
> +#define CLK_SET_RATE_GATE	BIT(0) /* must be gated across rate
> change */ +#define CLK_SET_PARENT_GATE	BIT(1) /* must be gated
> across re-parent */ #define CLK_SET_RATE_PARENT	BIT(2) /*
> propagate rate change up one level */ +#define
> CLK_IGNORE_UNUSED	BIT(3) /* do not gate even if unused */
> +				/* unused */
> +#define CLK_IS_BASIC		BIT(5) /* Basic clk, can't do a
> to_clk_foo() */ 

> +#define CLK_GET_RATE_NOCACHE	BIT(6) /* do not
> use the cached clk rate */ 

I guess that this is what your requested for the NOCACHE (to always
recalculate the rate).

> #define CLK_SET_RATE_NO_REPARENT BIT(7) /*
> don't re-parent on rate change */ +#define CLK_GET_ACCURACY_NOCACHE
> BIT(8) /* do not use the cached clk accuracy */ +#define
> CLK_RECALC_NEW_RATES	BIT(9) /* recalc rates after
> notifications */ +#define CLK_SET_RATE_UNGATE	BIT(10) /* clock
> needs to run to set rate */ +#define CLK_IS_CRITICAL
> BIT(11) /* do not gate, ever */ +/* parents need enable during
> gate/ungate, set rate and re-parent */ +#define
> CLK_OPS_PARENT_ENABLE	BIT(12) +/* duty cycle call may be
> forwarded to the parent clock */ +#define
> CLK_DUTY_CYCLE_PARENT	BIT(13) #define
> CLK_MUX_INDEX_ONE		BIT(0) #define
> CLK_MUX_INDEX_BIT		BIT(1)

Reviewed-by: Lukasz Majewski <lukma@denx.de>


Best regards,

Lukasz Majewski

--

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Patch
diff mbox series

diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index eac045c5f8..3458746a60 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -9,8 +9,29 @@ 
 #ifndef __LINUX_CLK_PROVIDER_H
 #define __LINUX_CLK_PROVIDER_H
 
+/*
+ * flags used across common struct clk.  these flags should only affect the
+ * top-level framework.  custom flags for dealing with hardware specifics
+ * belong in struct clk_foo
+ *
+ * Please update clk_flags[] in drivers/clk/clk.c when making changes here!
+ */
+#define CLK_SET_RATE_GATE	BIT(0) /* must be gated across rate change */
+#define CLK_SET_PARENT_GATE	BIT(1) /* must be gated across re-parent */
 #define CLK_SET_RATE_PARENT	BIT(2) /* propagate rate change up one level */
+#define CLK_IGNORE_UNUSED	BIT(3) /* do not gate even if unused */
+				/* unused */
+#define CLK_IS_BASIC		BIT(5) /* Basic clk, can't do a to_clk_foo() */
+#define CLK_GET_RATE_NOCACHE	BIT(6) /* do not use the cached clk rate */
 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
+#define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
+#define CLK_RECALC_NEW_RATES	BIT(9) /* recalc rates after notifications */
+#define CLK_SET_RATE_UNGATE	BIT(10) /* clock needs to run to set rate */
+#define CLK_IS_CRITICAL		BIT(11) /* do not gate, ever */
+/* parents need enable during gate/ungate, set rate and re-parent */
+#define CLK_OPS_PARENT_ENABLE	BIT(12)
+/* duty cycle call may be forwarded to the parent clock */
+#define CLK_DUTY_CYCLE_PARENT	BIT(13)
 
 #define CLK_MUX_INDEX_ONE		BIT(0)
 #define CLK_MUX_INDEX_BIT		BIT(1)