| Message ID | 20190426212112.5624-1-fancer.lancer@gmail.com |
|---|---|
| State | Changes Requested |
| Delegated to: | David Miller |
| Headers | show |
| Series | [v2,1/2] net: phy: realtek: Add rtl8211e rx/tx delays config | expand |
On Sat, Apr 27, 2019 at 12:21:11AM +0300, Serge Semin wrote: > There are two chip pins named TXDLY and RXDLY which actually adds the 2ns > delays to TXC and RXC for TXD/RXD latching. Alas this is the only > documented info regarding the RGMII timing control configurations the PHY > provides. It turns out the same settings can be setup via MDIO registers > hidden in the extension pages layout. Particularly the extension page 0xa4 > provides a register 0x1c, which bits 1 and 2 control the described delays. > They are used to implement the "rgmii-{id,rxid,txid}" phy-mode. > > The hidden RGMII configs register utilization was found in the rtl8211e > U-boot driver: > https://elixir.bootlin.com/u-boot/v2019.01/source/drivers/net/phy/realtek.c#L99 > > There is also a freebsd-folks discussion regarding this register: > https://reviews.freebsd.org/D13591 > > It confirms that the register bits field must control the so called > configuration pins described in the table 12-13 of the official PHY > datasheet: > 8:6 = PHY Address > 5:4 = Auto-Negotiation > 3 = Interface Mode Select > 2 = RX Delay > 1 = TX Delay > 0 = SELRGV > > Signed-off-by: Serge Semin <fancer.lancer@gmail.com> Hi Serge Next time please include a patch 0 containing a cover note explaining the who series. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Andrew
On Fri, Apr 26, 2019 at 11:40:50PM +0200, Andrew Lunn wrote: > On Sat, Apr 27, 2019 at 12:21:11AM +0300, Serge Semin wrote: > > There are two chip pins named TXDLY and RXDLY which actually adds the 2ns > > delays to TXC and RXC for TXD/RXD latching. Alas this is the only > > documented info regarding the RGMII timing control configurations the PHY > > provides. It turns out the same settings can be setup via MDIO registers > > hidden in the extension pages layout. Particularly the extension page 0xa4 > > provides a register 0x1c, which bits 1 and 2 control the described delays. > > They are used to implement the "rgmii-{id,rxid,txid}" phy-mode. > > > > The hidden RGMII configs register utilization was found in the rtl8211e > > U-boot driver: > > https://elixir.bootlin.com/u-boot/v2019.01/source/drivers/net/phy/realtek.c#L99 > > > > There is also a freebsd-folks discussion regarding this register: > > https://reviews.freebsd.org/D13591 > > > > It confirms that the register bits field must control the so called > > configuration pins described in the table 12-13 of the official PHY > > datasheet: > > 8:6 = PHY Address > > 5:4 = Auto-Negotiation > > 3 = Interface Mode Select > > 2 = RX Delay > > 1 = TX Delay > > 0 = SELRGV > > > > Signed-off-by: Serge Semin <fancer.lancer@gmail.com> > > > Hi Serge > > Next time please include a patch 0 containing a cover note explaining > the who series. > Sure as long as the patchset gets to be much bigger than two small patches with an obvious reason to be merged. > Reviewed-by: Andrew Lunn <andrew@lunn.ch> > Thanks.) -Sergey > Andrew
On 4/26/2019 4:45 PM, Serge Semin wrote: > On Fri, Apr 26, 2019 at 11:40:50PM +0200, Andrew Lunn wrote: >> On Sat, Apr 27, 2019 at 12:21:11AM +0300, Serge Semin wrote: >>> There are two chip pins named TXDLY and RXDLY which actually adds the 2ns >>> delays to TXC and RXC for TXD/RXD latching. Alas this is the only >>> documented info regarding the RGMII timing control configurations the PHY >>> provides. It turns out the same settings can be setup via MDIO registers >>> hidden in the extension pages layout. Particularly the extension page 0xa4 >>> provides a register 0x1c, which bits 1 and 2 control the described delays. >>> They are used to implement the "rgmii-{id,rxid,txid}" phy-mode. >>> >>> The hidden RGMII configs register utilization was found in the rtl8211e >>> U-boot driver: >>> https://elixir.bootlin.com/u-boot/v2019.01/source/drivers/net/phy/realtek.c#L99 >>> >>> There is also a freebsd-folks discussion regarding this register: >>> https://reviews.freebsd.org/D13591 >>> >>> It confirms that the register bits field must control the so called >>> configuration pins described in the table 12-13 of the official PHY >>> datasheet: >>> 8:6 = PHY Address >>> 5:4 = Auto-Negotiation >>> 3 = Interface Mode Select >>> 2 = RX Delay >>> 1 = TX Delay >>> 0 = SELRGV >>> >>> Signed-off-by: Serge Semin <fancer.lancer@gmail.com> >> >> >> Hi Serge >> >> Next time please include a patch 0 containing a cover note explaining >> the who series. >> > > Sure as long as the patchset gets to be much bigger than two small > patches with an obvious reason to be merged. netdev likes to have a cover letter for patch count >= 1, probably something to be added to netdev-FAQ.rst.
On Fri, Apr 26, 2019 at 08:11:50PM -0700, Florian Fainelli wrote: > > > On 4/26/2019 4:45 PM, Serge Semin wrote: > > On Fri, Apr 26, 2019 at 11:40:50PM +0200, Andrew Lunn wrote: > >> On Sat, Apr 27, 2019 at 12:21:11AM +0300, Serge Semin wrote: > >>> There are two chip pins named TXDLY and RXDLY which actually adds the 2ns > >>> delays to TXC and RXC for TXD/RXD latching. Alas this is the only > >>> documented info regarding the RGMII timing control configurations the PHY > >>> provides. It turns out the same settings can be setup via MDIO registers > >>> hidden in the extension pages layout. Particularly the extension page 0xa4 > >>> provides a register 0x1c, which bits 1 and 2 control the described delays. > >>> They are used to implement the "rgmii-{id,rxid,txid}" phy-mode. > >>> > >>> The hidden RGMII configs register utilization was found in the rtl8211e > >>> U-boot driver: > >>> https://elixir.bootlin.com/u-boot/v2019.01/source/drivers/net/phy/realtek.c#L99 > >>> > >>> There is also a freebsd-folks discussion regarding this register: > >>> https://reviews.freebsd.org/D13591 > >>> > >>> It confirms that the register bits field must control the so called > >>> configuration pins described in the table 12-13 of the official PHY > >>> datasheet: > >>> 8:6 = PHY Address > >>> 5:4 = Auto-Negotiation > >>> 3 = Interface Mode Select > >>> 2 = RX Delay > >>> 1 = TX Delay > >>> 0 = SELRGV > >>> > >>> Signed-off-by: Serge Semin <fancer.lancer@gmail.com> > >> > >> > >> Hi Serge > >> > >> Next time please include a patch 0 containing a cover note explaining > >> the who series. > >> > > > > Sure as long as the patchset gets to be much bigger than two small > > patches with an obvious reason to be merged. > > netdev likes to have a cover letter for patch count >= 1, probably > something to be added to netdev-FAQ.rst. > -- > Florian Hello Florian Really, even with count = 1? So just one patch with cover-letter? Doesn't it seem redundant since at least a single patch can be thoroughly described in it' commit message? -Sergey
> > >> Hi Serge > > >> > > >> Next time please include a patch 0 containing a cover note explaining > > >> the who series. > > >> > > > > > > Sure as long as the patchset gets to be much bigger than two small > > > patches with an obvious reason to be merged. > > > > netdev likes to have a cover letter for patch count >= 1, probably > > something to be added to netdev-FAQ.rst. > > -- > > Florian > > Hello Florian > Really, even with count = 1? So just one patch with cover-letter? Doesn't it > seem redundant since at least a single patch can be thoroughly described in > it' commit message? Hi Serge David workflow is to put the patch set into a branch, and then merge the branch into his master, using the cover note as the merge commit message. You occasionally see commit messages for count == 1, but not often. For > 1, if there is no cover note, somebody is likely to ask for one :-) Andrew
On 4/27/2019 12:44 AM, Serge Semin wrote: > On Fri, Apr 26, 2019 at 08:11:50PM -0700, Florian Fainelli wrote: >> >> >> On 4/26/2019 4:45 PM, Serge Semin wrote: >>> On Fri, Apr 26, 2019 at 11:40:50PM +0200, Andrew Lunn wrote: >>>> On Sat, Apr 27, 2019 at 12:21:11AM +0300, Serge Semin wrote: >>>>> There are two chip pins named TXDLY and RXDLY which actually adds the 2ns >>>>> delays to TXC and RXC for TXD/RXD latching. Alas this is the only >>>>> documented info regarding the RGMII timing control configurations the PHY >>>>> provides. It turns out the same settings can be setup via MDIO registers >>>>> hidden in the extension pages layout. Particularly the extension page 0xa4 >>>>> provides a register 0x1c, which bits 1 and 2 control the described delays. >>>>> They are used to implement the "rgmii-{id,rxid,txid}" phy-mode. >>>>> >>>>> The hidden RGMII configs register utilization was found in the rtl8211e >>>>> U-boot driver: >>>>> https://elixir.bootlin.com/u-boot/v2019.01/source/drivers/net/phy/realtek.c#L99 >>>>> >>>>> There is also a freebsd-folks discussion regarding this register: >>>>> https://reviews.freebsd.org/D13591 >>>>> >>>>> It confirms that the register bits field must control the so called >>>>> configuration pins described in the table 12-13 of the official PHY >>>>> datasheet: >>>>> 8:6 = PHY Address >>>>> 5:4 = Auto-Negotiation >>>>> 3 = Interface Mode Select >>>>> 2 = RX Delay >>>>> 1 = TX Delay >>>>> 0 = SELRGV >>>>> >>>>> Signed-off-by: Serge Semin <fancer.lancer@gmail.com> >>>> >>>> >>>> Hi Serge >>>> >>>> Next time please include a patch 0 containing a cover note explaining >>>> the who series. >>>> >>> >>> Sure as long as the patchset gets to be much bigger than two small >>> patches with an obvious reason to be merged. >> >> netdev likes to have a cover letter for patch count >= 1, probably >> something to be added to netdev-FAQ.rst. >> -- >> Florian > > Hello Florian > Really, even with count = 1? So just one patch with cover-letter? Doesn't it > seem redundant since at least a single patch can be thoroughly described in > it' commit message? I was off by one, it's for count > 1 that a cover letter is usually requested.
On Sat, Apr 27, 2019 at 05:21:09PM +0200, Andrew Lunn wrote: > > > >> Hi Serge > > > >> > > > >> Next time please include a patch 0 containing a cover note explaining > > > >> the who series. > > > >> > > > > > > > > Sure as long as the patchset gets to be much bigger than two small > > > > patches with an obvious reason to be merged. > > > > > > netdev likes to have a cover letter for patch count >= 1, probably > > > something to be added to netdev-FAQ.rst. > > > -- > > > Florian > > > > Hello Florian > > Really, even with count = 1? So just one patch with cover-letter? Doesn't it > > seem redundant since at least a single patch can be thoroughly described in > > it' commit message? > > Hi Serge > > David workflow is to put the patch set into a branch, and then merge > the branch into his master, using the cover note as the merge commit > message. > > You occasionally see commit messages for count == 1, but not often. > For > 1, if there is no cover note, somebody is likely to ask for one > :-) > > Andrew Hello Andrew and Florian Alright. I see your point. Though I am not really agree with it at this situation, the next version of the mini-patchset will be sent with a cover-letter as per maintainers request. Meanwhile lets put aside this discussion and get back to the topic-related one. Could you respond to the email I've sent in response to the Andrew's comment on the second patch of v2 duet? -Sergey
Hi, On Sat, Apr 27, 2019 at 12:21:11AM +0300, Serge Semin wrote: > There are two chip pins named TXDLY and RXDLY which actually adds the 2ns > delays to TXC and RXC for TXD/RXD latching. Alas this is the only > documented info regarding the RGMII timing control configurations the PHY > provides. It turns out the same settings can be setup via MDIO registers > hidden in the extension pages layout. Particularly the extension page 0xa4 > provides a register 0x1c, which bits 1 and 2 control the described delays. > They are used to implement the "rgmii-{id,rxid,txid}" phy-mode. > > The hidden RGMII configs register utilization was found in the rtl8211e > U-boot driver: > https://elixir.bootlin.com/u-boot/v2019.01/source/drivers/net/phy/realtek.c#L99 > > There is also a freebsd-folks discussion regarding this register: > https://reviews.freebsd.org/D13591 > > It confirms that the register bits field must control the so called > configuration pins described in the table 12-13 of the official PHY > datasheet: > 8:6 = PHY Address > 5:4 = Auto-Negotiation > 3 = Interface Mode Select > 2 = RX Delay > 1 = TX Delay > 0 = SELRGV > > Signed-off-by: Serge Semin <fancer.lancer@gmail.com> > Reviewed-by: Andrew Lunn <andrew@lunn.ch> This patch results in a crash when running arm:ast2500-evb in qemu. [ 4.894572] [00000000] *pgd=00000000 [ 4.895329] Internal error: Oops: 80000005 [#1] ARM [ 4.896066] CPU: 0 PID: 1 Comm: swapper Not tainted 5.1.0-09698-g1fb3b52 #1 [ 4.896364] Hardware name: Generic DT based system [ 4.896823] PC is at 0x0 [ 4.897037] LR is at phy_select_page+0x3c/0x7c Debugging shows that phydev->drv->write_page and phydev->drv->read_page are NULL, so the crash isn't entirely surprising. What I don't understand is how this can work in the first place. The modified entry in realtek_drvs[] doesn't have read_page/write_page functions defined, yet rtl8211e_config_init() depends on it. What am I missing here ? Thanks, Guenter
Hello Guenter, On Sun, May 12, 2019 at 10:41:32PM -0700, Guenter Roeck wrote: > Hi, > > On Sat, Apr 27, 2019 at 12:21:11AM +0300, Serge Semin wrote: > > There are two chip pins named TXDLY and RXDLY which actually adds the 2ns > > delays to TXC and RXC for TXD/RXD latching. Alas this is the only > > documented info regarding the RGMII timing control configurations the PHY > > provides. It turns out the same settings can be setup via MDIO registers > > hidden in the extension pages layout. Particularly the extension page 0xa4 > > provides a register 0x1c, which bits 1 and 2 control the described delays. > > They are used to implement the "rgmii-{id,rxid,txid}" phy-mode. > > > > The hidden RGMII configs register utilization was found in the rtl8211e > > U-boot driver: > > https://elixir.bootlin.com/u-boot/v2019.01/source/drivers/net/phy/realtek.c#L99 > > > > There is also a freebsd-folks discussion regarding this register: > > https://reviews.freebsd.org/D13591 > > > > It confirms that the register bits field must control the so called > > configuration pins described in the table 12-13 of the official PHY > > datasheet: > > 8:6 = PHY Address > > 5:4 = Auto-Negotiation > > 3 = Interface Mode Select > > 2 = RX Delay > > 1 = TX Delay > > 0 = SELRGV > > > > Signed-off-by: Serge Semin <fancer.lancer@gmail.com> > > Reviewed-by: Andrew Lunn <andrew@lunn.ch> > > This patch results in a crash when running arm:ast2500-evb in qemu. > > [ 4.894572] [00000000] *pgd=00000000 > [ 4.895329] Internal error: Oops: 80000005 [#1] ARM > [ 4.896066] CPU: 0 PID: 1 Comm: swapper Not tainted 5.1.0-09698-g1fb3b52 #1 > [ 4.896364] Hardware name: Generic DT based system > [ 4.896823] PC is at 0x0 > [ 4.897037] LR is at phy_select_page+0x3c/0x7c > > Debugging shows that phydev->drv->write_page and phydev->drv->read_page > are NULL, so the crash isn't entirely surprising. > > What I don't understand is how this can work in the first place. > The modified entry in realtek_drvs[] doesn't have read_page/write_page > functions defined, yet rtl8211e_config_init() depends on it. > What am I missing here ? > > Thanks, > Guenter Thanks for sending the report. The problem has already been fixed in the net: https://git.kernel.org/pub/scm/linux/kernel/git/davem/net.git/commit/?id=daf3ddbe11a2ff74c95bc814df8e5fe3201b4cb5 -Sergey
diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c index 10df52ccddfe..ab567a1923ad 100644 --- a/drivers/net/phy/realtek.c +++ b/drivers/net/phy/realtek.c @@ -23,11 +23,14 @@ #define RTL821x_INSR 0x13 +#define RTL821x_EXT_PAGE_SELECT 0x1e #define RTL821x_PAGE_SELECT 0x1f #define RTL8211F_INSR 0x1d #define RTL8211F_TX_DELAY BIT(8) +#define RTL8211E_TX_DELAY BIT(1) +#define RTL8211E_RX_DELAY BIT(2) #define RTL8201F_ISR 0x1e #define RTL8201F_IER 0x13 @@ -174,6 +177,52 @@ static int rtl8211f_config_init(struct phy_device *phydev) return phy_modify_paged(phydev, 0xd08, 0x11, RTL8211F_TX_DELAY, val); } +static int rtl8211e_config_init(struct phy_device *phydev) +{ + int ret, oldpage; + u16 val; + + /* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */ + switch (phydev->interface) { + case PHY_INTERFACE_MODE_RGMII: + val = 0; + break; + case PHY_INTERFACE_MODE_RGMII_ID: + val = RTL8211E_TX_DELAY | RTL8211E_RX_DELAY; + break; + case PHY_INTERFACE_MODE_RGMII_RXID: + val = RTL8211E_RX_DELAY; + break; + case PHY_INTERFACE_MODE_RGMII_TXID: + val = RTL8211E_TX_DELAY; + break; + default: /* the rest of the modes imply leaving delays as is. */ + return 0; + } + + /* According to a sample driver there is a 0x1c config register on the + * 0xa4 extension page (0x7) layout. It can be used to disable/enable + * the RX/TX delays otherwise controlled by hardware strobes. It can + * also be used to customize the whole configuration register: + * 8:6 = PHY Address, 5:4 = Auto-Negotiation, 3 = Interface Mode Select, + * 2 = RX Delay, 1 = TX Delay, 0 = SELRGV (see original PHY datasheet + * for details). + */ + oldpage = phy_select_page(phydev, 0x7); + if (oldpage < 0) + goto err_restore_page; + + ret = phy_write(phydev, RTL821x_EXT_PAGE_SELECT, 0xa4); + if (ret) + goto err_restore_page; + + ret = phy_modify(phydev, 0x1c, RTL8211E_TX_DELAY | RTL8211E_RX_DELAY, + val); + +err_restore_page: + return phy_restore_page(phydev, oldpage, ret); +} + static int rtl8211b_suspend(struct phy_device *phydev) { phy_write(phydev, MII_MMD_DATA, BIT(9)); @@ -257,6 +306,7 @@ static struct phy_driver realtek_drvs[] = { PHY_ID_MATCH_EXACT(0x001cc915), .name = "RTL8211E Gigabit Ethernet", .features = PHY_GBIT_FEATURES, + .config_init = &rtl8211e_config_init, .ack_interrupt = &rtl821x_ack_interrupt, .config_intr = &rtl8211e_config_intr, .suspend = genphy_suspend,
There are two chip pins named TXDLY and RXDLY which actually adds the 2ns delays to TXC and RXC for TXD/RXD latching. Alas this is the only documented info regarding the RGMII timing control configurations the PHY provides. It turns out the same settings can be setup via MDIO registers hidden in the extension pages layout. Particularly the extension page 0xa4 provides a register 0x1c, which bits 1 and 2 control the described delays. They are used to implement the "rgmii-{id,rxid,txid}" phy-mode. The hidden RGMII configs register utilization was found in the rtl8211e U-boot driver: https://elixir.bootlin.com/u-boot/v2019.01/source/drivers/net/phy/realtek.c#L99 There is also a freebsd-folks discussion regarding this register: https://reviews.freebsd.org/D13591 It confirms that the register bits field must control the so called configuration pins described in the table 12-13 of the official PHY datasheet: 8:6 = PHY Address 5:4 = Auto-Negotiation 3 = Interface Mode Select 2 = RX Delay 1 = TX Delay 0 = SELRGV Signed-off-by: Serge Semin <fancer.lancer@gmail.com> --- Changelog v2 - Disable delays for rgmii mode and leave them as is for the rest of the modes. - Remove genphy_config_init() invocation. It's redundant for rtl8211e phy. - Fix confused return value checking of extended-page selector call. - Fix commit message typos. --- drivers/net/phy/realtek.c | 50 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+)