From patchwork Tue Aug 9 07:58:23 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Koen Beel X-Patchwork-Id: 109153 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from merlin.infradead.org (merlin.infradead.org [IPv6:2001:4978:20e::2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 9A73CB6F8C for ; Tue, 9 Aug 2011 17:58:41 +1000 (EST) Received: from canuck.infradead.org ([2001:4978:20e::1]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QqhCq-0001FT-Kx; Tue, 09 Aug 2011 07:58:32 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1QqhCq-0006eK-4H; Tue, 09 Aug 2011 07:58:32 +0000 Received: from mail-wy0-f177.google.com ([74.125.82.177]) by canuck.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QqhCl-0006dv-I9; Tue, 09 Aug 2011 07:58:29 +0000 Received: by wyh11 with SMTP id 11so192179wyh.36 for ; Tue, 09 Aug 2011 00:58:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=FAvj9n8qbvNeq/b1t0Dn45pYiQYsjAgifNVtGsY5UYo=; b=kqPrFXoy5Dj/8UMAivURXBfy5p/mJfLU2mBqp/wQFV/KP6dH08NxaiK10pf654b/P5 ZCKw0vyoK/2FPqQcD8Goma8ARMh877SLMq0MzMqCJgc0GnKiVUBcQVfQ5C3tM4YAcwJP bBBErGuaEKKbDzpH1lX61FXnA6FNfxXAxil/0= MIME-Version: 1.0 Received: by 10.216.134.82 with SMTP id r60mr4066141wei.13.1312876704277; Tue, 09 Aug 2011 00:58:24 -0700 (PDT) Received: by 10.216.156.14 with HTTP; Tue, 9 Aug 2011 00:58:23 -0700 (PDT) In-Reply-To: <4E40D563.2090202@freescale.com> References: <20110805135133.GA26981@pengutronix.de> <4E3F8087.6070206@freescale.com> <4E3FBC75.7010703@freescale.com> <4E40D563.2090202@freescale.com> Date: Tue, 9 Aug 2011 09:58:23 +0200 Message-ID: Subject: Re: GPMI-NAND Status? From: Koen Beel To: Huang Shijie X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110809_035828_007031_6E0AAEBA X-CRM114-Status: GOOD ( 35.26 ) X-Spam-Score: -0.8 (/) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (-0.8 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (koen.beel.barco[at]gmail.com) -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [74.125.82.177 listed in list.dnswl.org] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature Cc: Wolfram Sang , linux-mtd@lists.infradead.org, Shawn Guo , shijie8@gmail.com, linux-arm-kernel@lists.infradead.org, =?UTF-8?Q?Lothar_Wa=C3=9Fmann?= X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-mtd-bounces@lists.infradead.org Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Hi, On Tue, Aug 9, 2011 at 8:36 AM, Huang Shijie wrote: > Hi Koen: >> >> Hi, >> >> On Mon, Aug 8, 2011 at 12:37 PM, Huang Shijie >>  wrote: >>> >>> Hi, >>>> >>>> On my target, the mxs-dma is working for sdio until the gpmi-nand >>>> gives a timeout. After that the dma for sdio is *not fully* working >>>> anymore. >>>> >>> We need more log in following aspects: >>> [1] apbh-dma registers >>> [2] clk registers >>> [3] gpmi registers >>> >>> Please git-apply the patch in the attachment. >>> It will print out more DMA information WHEN dma-timeout occur. >> >> Don't get it. What exactly are you trying to dump? >> This patch dumps CTRL0, CTRL1, CTRL2, DEVSEL but also some registers >> of APBH channel0 which is reserved.... > > sorry, I intended to print out the channel 4(NAND_DEVICE0). > > I want to know that: >  When the dma timeout occurs, whether it caused by the GPMI or by the DMA > itself. Ok, I was a little confused about the addresses, but it seems like you are using mx28 (and corresponding addresses). APBH dma for mx23 has different address according to the datasheet. So I adjusted the patch a little for mx23, see attachment. Here is the log with some comments added on the dma. # ubiformat /dev/mtd1 ubiformat: mtd1 (nand), size 20971520 bytes (20.0 MiB), 40 eraseblocks of 524288 bytes (512.0 KiB), min. I/O size 4096 bytes libscan: scanning eraseblock 0 -- 2 % complete [ 86.720000] [ start_dma_without_bch_irq : 393 ] DMA timeout, last DMA :1 [ 86.720000] ------------------------DMA DUMP BEGIN ---------- [ 86.730000] APBH REG :0 : 30000000 // -> HW_APBH_CTRL0: AHB_BURST8_EN, APB_BURST4_EN [ 86.730000] APBH REG :10 : 00FF0000 // -> HW_APBH_CTRL1: CHX_CMDCMPLT_IRQ_EN, no cmdcmplt_irq [ 86.740000] APBH REG :20 : 00000000 // -> HW_APBH_CTRL2: no error_irq [ 86.740000] APBH REG :30 : 00000000 // -> HW_APBH_DEVSEL: "N/A for apbh bridge dma." [ 86.750000] APBH CH4 REG :200 : 418D7098 // executing last dma command of command chain (see below) [ 86.750000] APBH CH4 REG :210 : 00000000 // no next command, ok [ 86.750000] APBH CH4 REG :220 : 000001C8 // HW_APBH_CH4_CMD: COMMAND = NO DMA TRANSFER, IRQONCMPLT, WAIT4ENDCMD, SEMAPHORE, HALTONTERMINATE [ 86.760000] APBH CH4 REG :230 : 00000000 // HW_APBH_CH4_BAR: "Address of system memory buffer to be read or written over the AHB bus." -> strange value ... [ 86.760000] APBH CH4 REG :240 : 00010000 // HW_APBH_CH4_SEMA: semaphore counter is 1 [ 86.770000] APBH CH4 REG :250 : 03A00015 // HW_APBH_CH4_DEBUG1: LOCK, NEXTCMDADDRVALID, RD_FIFO_EMPTY, WR_FIFO_EMPTY, STATEMACHINE = "WAIT_END = 0x15 When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete." [ 86.770000] APBH CH4 REG :260 : 00000000 // -> HW_APBH_CH4_DEBUG2: no apb of ahb bytes remaining for transfer [ 86.780000] [ 0 ] : ME : 418d7000, next : 418d704c, bits : 00002304, bytes : 00000000, buf : 00000000 [ 86.790000] [ 0 ] PIO[0] : 03800000 [ 86.790000] [ 0 ] PIO[1] : 00000000 [ 86.800000] [ 0 ] PIO[2] : 00000000 [ 86.800000] [ 1 ] : ME : 418d704c, next : 418d7098, bits : 00006304, bytes : 00000001, buf : 4181b000 [ 86.810000] [ 1 ] PIO[0] : 018010da [ 86.810000] [ 1 ] PIO[1] : 00000000 [ 86.820000] [ 1 ] PIO[2] : 000011ff [ 86.820000] [ 2 ] : ME : 418d7098, next : 00000000, bits : 000023c8, bytes : 00000000, buf : 00000000 [ 86.830000] [ 2 ] PIO[0] : 038010da [ 86.840000] [ 2 ] PIO[1] : 00000000 [ 86.840000] [ 2 ] PIO[2] : 00000000 [ 86.840000] ------------------------DMA DUMP END ------------ [ 86.850000] [ gpmi_show_regs : 076 ] -------------- Show GPMI registers ---------- [ 86.860000] [ gpmi_show_regs : 079 ] offset 0x000 : 0x238010da [ 86.870000] [ gpmi_show_regs : 079 ] offset 0x010 : 0x00000000 [ 86.870000] [ gpmi_show_regs : 079 ] offset 0x020 : 0x000011ff [ 86.880000] [ gpmi_show_regs : 079 ] offset 0x030 : 0x000010da [ 86.890000] [ gpmi_show_regs : 079 ] offset 0x040 : 0x40f0c480 [ 86.890000] [ gpmi_show_regs : 079 ] offset 0x050 : 0x40f09000 [ 86.900000] [ gpmi_show_regs : 079 ] offset 0x060 : 0x0004000c [ 86.910000] [ gpmi_show_regs : 079 ] offset 0x070 : 0x00010203 [ 86.910000] [ gpmi_show_regs : 079 ] offset 0x080 : 0x05000000 [ 86.920000] [ gpmi_show_regs : 079 ] offset 0x090 : 0x09020101 [ 86.920000] [ gpmi_show_regs : 079 ] offset 0x0a0 : 0x00000030 [ 86.930000] [ gpmi_show_regs : 079 ] offset 0x0b0 : 0x80000010 [ 86.940000] [ gpmi_show_regs : 079 ] offset 0x0c0 : 0x100000ba [ 86.940000] [ gpmi_show_regs : 079 ] offset 0x0d0 : 0x03000000 [ 86.950000] [ gpmi_show_regs : 081 ] -------------- Show GPMI registers end ---------- [ 86.960000] Kernel panic - not syncing: -----------DMA FAILED------------------ Br, Koen > > > Please try the new patch. > > Best Regards > Huang Shijie >> >> Then it prints some debug info on channel 1 (ssp1) and then alle >> channel 2 register except the debug register (ssp2 = not used here). >> >> What info do you need? >> >> Br, >> Koen >> >>> Best Regards >>> Huang Shijie >>> >> _______________________________________________ >> linux-arm-kernel mailing list >> linux-arm-kernel@lists.infradead.org >> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel >> > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel > > From 457e7328e0b11e7fc88884412952038a9cae5248 Mon Sep 17 00:00:00 2001 From: Koen Beel Date: Tue, 9 Aug 2011 09:56:42 +0200 Subject: [PATCH 8/8] Added extra dma log for ch4 (nand0). --- drivers/dma/mxs-dma.c | 37 +++++++++++++++++++++++++++++++- drivers/mtd/nand/gpmi-nand/gpmi-nand.c | 2 + 2 files changed, 38 insertions(+), 1 deletions(-) diff --git a/drivers/dma/mxs-dma.c b/drivers/dma/mxs-dma.c index 88aad4f..09c6c7b 100644 --- a/drivers/dma/mxs-dma.c +++ b/drivers/dma/mxs-dma.c @@ -130,6 +130,7 @@ struct mxs_dma_engine { struct mxs_dma_chan mxs_chans[MXS_DMA_CHANNELS]; }; +struct mxs_dma_chan *g_mxs_chan; static void mxs_dma_reset_chan(struct mxs_dma_chan *mxs_chan) { struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; @@ -239,6 +240,7 @@ static dma_cookie_t mxs_dma_tx_submit(struct dma_async_tx_descriptor *tx) struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(tx->chan); mxs_dma_enable_chan(mxs_chan); + g_mxs_chan = mxs_chan; return mxs_dma_assign_cookie(mxs_chan); } @@ -370,6 +372,7 @@ static void mxs_dma_free_chan_resources(struct dma_chan *chan) clk_disable(mxs_dma->clk); } +static int idx; static struct dma_async_tx_descriptor *mxs_dma_prep_slave_sg( struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len, enum dma_data_direction direction, @@ -381,7 +384,6 @@ static struct dma_async_tx_descriptor *mxs_dma_prep_slave_sg( struct scatterlist *sg; int i, j; u32 *pio; - static int idx; if (mxs_chan->status == DMA_IN_PROGRESS && !append) return NULL; @@ -606,6 +608,39 @@ err_out: return ret; } + +void dump_dma_reg(void) +{ + int i; + u32 stat1; + + struct mxs_dma_chan *mxs_chan = g_mxs_chan; + struct mxs_dma_engine *g_mxs_dma = mxs_chan->mxs_dma; + struct mxs_dma_ccw *ccw; + + printk("------------------------DMA DUMP BEGIN ----------\n"); + for (i = 0; i < 4; i++) { + stat1 = readl(g_mxs_dma->base + 0x10 * i); + printk("APBH REG :%x : %.8X\n", 0x10 * i, stat1); + } + for (i = 0; i < 7; i++) { + stat1 = readl(g_mxs_dma->base + 0x10 * i + 0x200); + printk("APBH CH4 REG :%x : %.8X\n", 0x10 * i + 0x200, stat1); + } + + for (i = 0; i < idx; i++) { + int j; + + ccw = &mxs_chan->ccw[i]; + printk("[ %d ] : ME : %.8x, next : %.8x, bits : %.8x, bytes : %.8x, buf : %.8x\n", + i, mxs_chan->ccw_phys + sizeof(*ccw) * i, + ccw->next, ccw->bits, ccw->xfer_bytes, ccw->bufaddr); + for (j = 0; j < 3; j++) + printk("[ %d ] PIO[%d] : %.8x\n", i, j, ccw->pio_words[j]); + } + printk("------------------------DMA DUMP END ------------\n"); +} + static int __init mxs_dma_probe(struct platform_device *pdev) { const struct platform_device_id *id_entry = diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c index 1c2cbc5..3d6895b 100644 --- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c +++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c @@ -378,6 +378,7 @@ int start_dma_without_bch_irq(struct gpmi_nand_data *this, { struct completion *dma_c = &this->dma_done; int err; + extern void dump_dma_reg(void); init_completion(dma_c); @@ -391,6 +392,7 @@ int start_dma_without_bch_irq(struct gpmi_nand_data *this, if (err) { pr_info("DMA timeout, last DMA :%d\n", this->last_dma_type); if (gpmi_debug & GPMI_DEBUG_CRAZY) { + dump_dma_reg(); gpmi_show_regs(this); panic("-----------DMA FAILED------------------"); } -- 1.7.4.1