diff mbox series

[16/26] target/arm: Move NS TBFLAG from bit 19 to bit 6

Message ID 20190416125744.27770-17-peter.maydell@linaro.org
State New
Headers show
Series target/arm: Implement M profile floating point | expand

Commit Message

Peter Maydell April 16, 2019, 12:57 p.m. UTC 
Move the NS TBFLAG down from bit 19 to bit 6, which has not
been used since commit c1e3781090b9d36c60 in 2015, when we
started passing the entire MMU index in the TB flags rather
than just a 'privilege level' bit.

This rearrangement is not strictly necessary, but means that
we can put M-profile-only bits next to each other rather
than scattered across the flag word.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

Comments

Richard Henderson April 23, 2019, 11:47 p.m. UTC | #1 
On 4/16/19 5:57 AM, Peter Maydell wrote:
> Move the NS TBFLAG down from bit 19 to bit 6, which has not
> been used since commit c1e3781090b9d36c60 in 2015, when we
> started passing the entire MMU index in the TB flags rather
> than just a 'privilege level' bit.
> 
> This rearrangement is not strictly necessary, but means that
> we can put M-profile-only bits next to each other rather
> than scattered across the flag word.
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
>  target/arm/cpu.h | 11 ++++++-----
>  1 file changed, 6 insertions(+), 5 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~
diff mbox series

Patch

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 0e0cb6b2271..c436f628987 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3139,6 +3139,12 @@  FIELD(TBFLAG_ANY, BE_DATA, 23, 1)
 FIELD(TBFLAG_A32, THUMB, 0, 1)
 FIELD(TBFLAG_A32, VECLEN, 1, 3)
 FIELD(TBFLAG_A32, VECSTRIDE, 4, 2)
+/*
+ * Indicates whether cp register reads and writes by guest code should access
+ * the secure or nonsecure bank of banked registers; note that this is not
+ * the same thing as the current security state of the processor!
+ */
+FIELD(TBFLAG_A32, NS, 6, 1)
 FIELD(TBFLAG_A32, VFPEN, 7, 1)
 FIELD(TBFLAG_A32, CONDEXEC, 8, 8)
 FIELD(TBFLAG_A32, SCTLR_B, 16, 1)
@@ -3146,11 +3152,6 @@  FIELD(TBFLAG_A32, SCTLR_B, 16, 1)
  * checks on the other bits at runtime
  */
 FIELD(TBFLAG_A32, XSCALE_CPAR, 17, 2)
-/* Indicates whether cp register reads and writes by guest code should access
- * the secure or nonsecure bank of banked registers; note that this is not
- * the same thing as the current security state of the processor!
- */
-FIELD(TBFLAG_A32, NS, 19, 1)
 /* For M profile only, Handler (ie not Thread) mode */
 FIELD(TBFLAG_A32, HANDLER, 21, 1)
 /* For M profile only, whether we should generate stack-limit checks */