Message ID | 20190411170355.6882-2-mmaddireddy@nvidia.com |
---|---|
State | Changes Requested |
Headers | show
Return-Path: <linux-tegra-owner@vger.kernel.org> X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=<UNKNOWN>) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="Hb8PTA75"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44g6ns39sqz9s0W for <incoming@patchwork.ozlabs.org>; Fri, 12 Apr 2019 03:04:33 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726603AbfDKREb (ORCPT <rfc822;incoming@patchwork.ozlabs.org>); Thu, 11 Apr 2019 13:04:31 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:11620 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726106AbfDKREb (ORCPT <rfc822;linux-tegra@vger.kernel.org>); Thu, 11 Apr 2019 13:04:31 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id <B5caf73a30000>; Thu, 11 Apr 2019 10:04:35 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 11 Apr 2019 10:04:30 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 11 Apr 2019 10:04:30 -0700 Received: from HQMAIL103.nvidia.com (172.20.187.11) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 11 Apr 2019 17:04:28 +0000 Received: from manikanta-bm2.nvidia.com (172.20.13.39) by HQMAIL.nvidia.com (172.20.187.11) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Thu, 11 Apr 2019 17:04:25 +0000 From: Manikanta Maddireddy <mmaddireddy@nvidia.com> To: <thierry.reding@gmail.com>, <bhelgaas@google.com>, <robh+dt@kernel.org>, <mark.rutland@arm.com>, <jonathanh@nvidia.com>, <lorenzo.pieralisi@arm.com>, <vidyas@nvidia.com> CC: <linux-tegra@vger.kernel.org>, <linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>, Manikanta Maddireddy <mmaddireddy@nvidia.com> Subject: [PATCH 01/30] soc/tegra: pmc: Export tegra_powergate_power_on() Date: Thu, 11 Apr 2019 22:33:26 +0530 Message-ID: <20190411170355.6882-2-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190411170355.6882-1-mmaddireddy@nvidia.com> References: <20190411170355.6882-1-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1555002275; bh=WqS9g7jfUwx32LOnIWwTeOsXW9/8fLErBOIuIMjA8YM=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=Hb8PTA75p5IpHUtuuHLWZNXYoikDTlEB4+EPu1EAR0wF+rroN73reI53QdATKiyf5 0ye+S29kRBNCCblQDPcRveOBp2z7v2AYBNmLILLstRDdHeBKCbxw5eBc1AVAMcPpx9 PwJedK2udUBXf7y2vJqaeWlkAcZHlqEyPG+7mbs0gg0IqgTus3/QvNFbE4hIwLPr+l buR45uJIEo0Tsb9DgCscSvDkLOD0zQ2LvmB3wr8vVaNCbANX3Lrk0U8ubx2bDx4eS2 /NRI4hI09cPBHYp4dO2Opu4xvkr/voVFYuMLBrjWjxI7P3SnSZ43NXhRNpTThnDINg Oei5LedSCfpmw== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: <linux-tegra.vger.kernel.org> X-Mailing-List: linux-tegra@vger.kernel.org |
Series |
Enable Tegra PCIe root port features
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expand
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diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 0c5f79528e5f..cb3de81348bd 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -701,6 +701,7 @@ int tegra_powergate_power_on(unsigned int id) return tegra_powergate_set(pmc, id, true); } +EXPORT_SYMBOL(tegra_powergate_power_on); /** * tegra_powergate_power_off() - power off partition
tegra_powergate_sequence_power_up() powers up partition and also enables clock & reset. However if a controller like PCIe have multiple clocks & resets and they need to be enabled in a sequence, driver has to use standalone function tegra_powergate_power_on() to power up partition. Export tegra_powergate_power_on() to allow Tegra controller drivers to unpower gate partition independent to clock & reset. Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com> --- drivers/soc/tegra/pmc.c | 1 + 1 file changed, 1 insertion(+)