diff mbox series

[V7,3/4] arm64: dts: freescale: imx8qxp: enable scu general irq channel

Message ID 1554785675-8090-3-git-send-email-Anson.Huang@nxp.com
State Not Applicable, archived
Headers show
Series [V7,1/4] dt-bindings: fsl: scu: add general interrupt support | expand

Checks

Context Check Description
robh/checkpatch success

Commit Message

Anson Huang April 9, 2019, 5 a.m. UTC 
On i.MX8QXP, SCU uses MU1 general interrupt channel #3 to notify
user for IRQs of RTC alarm, thermal alarm and WDOG etc., mailbox
RX doorbell mode is used for this function, this patch adds
support for it.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
---
No changes.
---
 arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

Comments

Shawn Guo April 11, 2019, 7:34 a.m. UTC | #1 
On Tue, Apr 09, 2019 at 05:00:01AM +0000, Anson Huang wrote:
> On i.MX8QXP, SCU uses MU1 general interrupt channel #3 to notify
> user for IRQs of RTC alarm, thermal alarm and WDOG etc., mailbox
> RX doorbell mode is used for this function, this patch adds
> support for it.
> 
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>

Prefix 'arm64: dts: imx8qxp:' would be good enough, and no need for
'freescale' in there.

I fixed it up and applied the patch.

Shawn
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index 0cb9398..70ef3db 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -21,6 +21,7 @@ 
 		mmc1 = &usdhc2;
 		mmc2 = &usdhc3;
 		serial0 = &adma_lpuart0;
+		mu1 = &lsio_mu1;
 	};
 
 	cpus {
@@ -117,7 +118,8 @@ 
 	scu {
 		compatible = "fsl,imx-scu";
 		mbox-names = "tx0", "tx1", "tx2", "tx3",
-			     "rx0", "rx1", "rx2", "rx3";
+			     "rx0", "rx1", "rx2", "rx3",
+			     "gip3";
 		mboxes = <&lsio_mu1 0 0
 			  &lsio_mu1 0 1
 			  &lsio_mu1 0 2
@@ -125,7 +127,8 @@ 
 			  &lsio_mu1 1 0
 			  &lsio_mu1 1 1
 			  &lsio_mu1 1 2
-			  &lsio_mu1 1 3>;
+			  &lsio_mu1 1 3
+			  &lsio_mu1 3 3>;
 
 		clk: clock-controller {
 			compatible = "fsl,imx8qxp-clk";