| Message ID | 1312299792-16415-12-git-send-email-nagabhushana.netagunte@ti.com |
|---|---|
| State | Changes Requested |
| Headers | show |
Dear nagabhushana.netagunte@ti.com, In message <1312299792-16415-12-git-send-email-nagabhushana.netagunte@ti.com> you wrote: > From: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com> > > AHCLKR/UART1_RTS/GP0[11] pin needs to be configured for > NOR to work on Rev.3 EVM. When GP0[11] is low, > the SD0 interface will not work, but NOR flash will. > > Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com> > Signed-off-by: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com> > --- > arch/arm/include/asm/arch-davinci/hardware.h | 5 ++++- > board/davinci/da8xxevm/da850evm.c | 15 +++++++++++++++ > 2 files changed, 19 insertions(+), 1 deletions(-) ... > +#ifdef CONFIG_USE_NOR > + /* Set the GPIO direction as output */ > + val = readl(GPIO_BANK0_REG_DIR_ADDR); > + val &= ~(0x01 << 11); > + writel(val, GPIO_BANK0_REG_DIR_ADDR); > + > + /* Set the output as low */ > + val = readl(GPIO_BANK0_REG_SET_ADDR); > + val |= (0x01 << 11); > + writel(val, GPIO_BANK0_REG_CLR_ADDR); > +#endif Please use standard clrbits / setbits macros instead. Best regards, Wolfgang Denk
Denk, Thanks a lot for comments. I will incorporate changes suggested by you. Regards, Nag On Tue, Aug 02, 2011 at 22:02:12, Wolfgang Denk wrote: > Dear nagabhushana.netagunte@ti.com, > > In message <1312299792-16415-12-git-send-email-nagabhushana.netagunte@ti.com> you wrote: > > From: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com> > > > > AHCLKR/UART1_RTS/GP0[11] pin needs to be configured for NOR to work on > > Rev.3 EVM. When GP0[11] is low, the SD0 interface will not work, but > > NOR flash will. > > > > Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com> > > Signed-off-by: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com> > > --- > > arch/arm/include/asm/arch-davinci/hardware.h | 5 ++++- > > board/davinci/da8xxevm/da850evm.c | 15 +++++++++++++++ > > 2 files changed, 19 insertions(+), 1 deletions(-) > ... > > +#ifdef CONFIG_USE_NOR > > + /* Set the GPIO direction as output */ > > + val = readl(GPIO_BANK0_REG_DIR_ADDR); > > + val &= ~(0x01 << 11); > > + writel(val, GPIO_BANK0_REG_DIR_ADDR); > > + > > + /* Set the output as low */ > > + val = readl(GPIO_BANK0_REG_SET_ADDR); > > + val |= (0x01 << 11); > > + writel(val, GPIO_BANK0_REG_CLR_ADDR); #endif > > Please use standard clrbits / setbits macros instead. > > > > Best regards, > > Wolfgang Denk > > -- > DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany > Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de "If that makes any sense to you, you have a big problem." > -- C. Durance, Computer Science 234 >
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h index 5498042..fda8203 100644 --- a/arch/arm/include/asm/arch-davinci/hardware.h +++ b/arch/arm/include/asm/arch-davinci/hardware.h @@ -157,7 +157,10 @@ typedef volatile unsigned int * dv_reg_p; #define HOST1CFG (DAVINCI_BOOTCFG_BASE + 0x44) #define PSC0_MDCTL (DAVINCI_PSC0_BASE + 0xa00) - +#define GPIO_BANK0_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x10) +#define GPIO_BANK0_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x14) +#define GPIO_BANK0_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x18) +#define GPIO_BANK0_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x1c) #define GPIO_BANK2_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x38) #define GPIO_BANK2_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x3c) #define GPIO_BANK2_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x40) diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c index 64ff566..a0b4425 100644 --- a/board/davinci/da8xxevm/da850evm.c +++ b/board/davinci/da8xxevm/da850evm.c @@ -111,6 +111,8 @@ const struct pinmux_config nand_pins[] = { #elif defined(CONFIG_USE_NOR) /* NOR pin muxer settings */ const struct pinmux_config nor_pins[] = { + /* GP0[11] is required for NOR to work on Rev 3 EVMs */ + { pinmux(0), 8, 4 }, /* GP0[11] */ { pinmux(5), 1, 6 }, { pinmux(6), 1, 6 }, { pinmux(7), 1, 0 }, @@ -230,6 +232,7 @@ u32 get_board_rev(void) int board_init(void) { + u32 val; #ifndef CONFIG_USE_IRQ irq_init(); #endif @@ -277,6 +280,18 @@ int board_init(void) if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes))) return 1; +#ifdef CONFIG_USE_NOR + /* Set the GPIO direction as output */ + val = readl(GPIO_BANK0_REG_DIR_ADDR); + val &= ~(0x01 << 11); + writel(val, GPIO_BANK0_REG_DIR_ADDR); + + /* Set the output as low */ + val = readl(GPIO_BANK0_REG_SET_ADDR); + val |= (0x01 << 11); + writel(val, GPIO_BANK0_REG_CLR_ADDR); +#endif + #ifdef CONFIG_DRIVER_TI_EMAC if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0) return 1;