| Message ID | 1554423259-26056-10-git-send-email-skomatineni@nvidia.com |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | [V2,01/20] spi: tegra114: fix PIO transfer | expand |
On Thu, Apr 04, 2019 at 05:14:09PM -0700, Sowjanya Komatineni wrote: > spi-lsbyte-first optional property allows SPI slaves to choose byte > order of little endian for transfers. Why make this a DT property - surely it's either a fixed property of the relevant devices if they are LSB first (in which case we should know we can use it from the device) or it's something that the driver for the device can just vary at runtime?
diff --git a/Documentation/devicetree/bindings/spi/spi-bus.txt b/Documentation/devicetree/bindings/spi/spi-bus.txt index 1f6e86f787ef..b455c24a80df 100644 --- a/Documentation/devicetree/bindings/spi/spi-bus.txt +++ b/Documentation/devicetree/bindings/spi/spi-bus.txt @@ -71,6 +71,7 @@ All slave nodes can contain the following optional properties: active high. - spi-3wire - Empty property indicating device requires 3-wire mode. - spi-lsb-first - Empty property indicating device requires LSB first mode. +- spi-lsbyte-first - Empty property indicating device requires LSByte first mode. - spi-tx-bus-width - The bus width (number of data wires) that is used for MOSI. Defaults to 1 if not present. - spi-rx-bus-width - The bus width (number of data wires) that is used for MISO.
spi-lsbyte-first optional property allows SPI slaves to choose byte order of little endian for transfers. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> --- Documentation/devicetree/bindings/spi/spi-bus.txt | 1 + 1 file changed, 1 insertion(+)